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Initial commit
author Michael Pavone <pavone@retrodev.com>
date Fri, 20 Jan 2017 00:22:15 -0800
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files sega_vdp.html
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+<!DOCTYPE html>
+<html>
+<head>
+	<title>Sega Home System VDP Reference</title>
+	<style>
+body {
+	font-family: sans-serif;
+}
+table {
+	border-color: black;
+	border-bottom-style: solid;
+	border-bottom-width: 1px;
+	border-right-width: 1px;
+	border-right-style: solid;
+}
+tr > * {
+	border-top-width: 1px;
+	border-left-width: 1px;
+	border-top-style: solid;
+	border-left-style: solid;
+}
+
+p {
+	max-width: 70em;
+}
+	</style>
+</head>
+<body>
+	<h1>Sega Home Console VDP Documentation</h1>
+	<h2>Overview</h2>
+	<p>
+		This document describes the operation of the family of related video display
+		processors used by Sega's 8 and 16-bit home game consoles.
+	<h2>Video Modes</h2>
+	
+	<h3>Mode 0 - Graphics I</h3>
+	<h4>Availabiltiy</h4>
+	<p>
+		This mode is available on the Mark III, Master System, Game Gear in addition to
+		systems that use the TMS9918 and derivatives including early systems from Sega
+		(the SG-1000 and SC-3000) as well as MSX computers and the Collecovision game
+		console.
+	</p>
+	</h4>
+	<h3>Mode 1 - Text</h3>
+	<h4>Availabiltiy</h4>
+	<p>
+		This mode is available on the Mark III, Master System, Game Gear in addition to
+		systems that use the TMS9918 and derivatives including early systems from Sega
+		(the SG-1000 and SC-3000) as well as MSX computers and the Collecovision game
+		console.
+	</p>
+	</h4>
+	<h3>Mode 2 - Graphics II</h3>
+	<h4>Availabiltiy</h4>
+	<p>
+		This mode is available on the Mark III, Master System, Game Gear in addition to
+		systems that use the TMS9918A and derivatives including early systems from Sega
+		(the SG-1000 and SC-3000) as well as MSX computers, the Collecovision game
+		console and TI-99/4A. It is not available on systems with the original TMS9918
+		like the TI-99/4.
+	</p>
+	</h4>
+	<h3>Mode 3 - Multicolor</h3>
+	<h4>Availabiltiy</h4>
+	<p>
+		This mode is available on the Mark III, Master System, Game Gear in addition to
+		systems that use the TMS9918 and derivatives including early systems from Sega
+		(the SG-1000 and SC-3000) as well as MSX computers and the Collecovision game
+		console.
+	</p>
+	</h4>
+	<h3>Mode 4 (primary SMS mode)</h3>
+	<h4>Availabiltiy</h4>
+	<p>
+		Mode 4 is available on the Mark III, Master System, Game Gear and Genesis/Megadrive.
+	</p>
+	<h4>Capabilities</h4>
+	<p>
+		TODO: Fill me in
+	</p>
+	<h4>Selection and Resolution Control</h4>
+	<p>
+		Mode 4 is enabled by setting bit 2 in <a href="#reg0">$00 - Mode Set Register 1</a>.
+		On the Mark III and SMS 1, only one resolution is available 256x192. The Game Gear
+		uses this same resolution, but crops the visible display area to 160x144.
+	</p>
+	<h3>Mode 5 (primary Genesis/Megadrive mode)</h3>
+	<h4>Availability</h4>
+	<p>
+		Mode 5 is available only on the Genesis/Megadrive and systems derived from Genesis
+		hardware like the System C, Mega Tech and Mega Play arcade boards.
+	</p>
+	<h4>Capabilities</h4>
+	<p>
+		Mode 5 is the primary mode used by software on the Genesis/Megadrive. It provides 2 
+		independently scrollable background planes and 64 or 80 sprites dependign on the
+		horizontal resolution. Background planes can be up to 128x64 or 64x128 tiles. One of
+		the background planes (Plane A) can be replaced with the special Window plane for a
+		portion of the screen. Sprites can range from 1 to 4 tiles in size both vertically
+		and horizontally. Up to 16 or 20 sprites can be displayed and up to 256 or 320 sprite
+		pixels can be drawn per line, again depending on the horizontal resolution selected. 
+	</p>
+	<p>
+		Tiles in this mode are 8 by 8 pixels in size with a depth of 4 bits per pixel arranged
+		in a chunky configuration. This results in a size of 32 bytes with the first byte
+		containing the two left most pixels of the first row and the last byte containing the
+		two right most pixels of the last row. Each 4 bit value is used as an index into one
+		of 4 16-color palettes.
+	</p>
+	<h4>Selection and Resolution Control</h4>
+	<p>
+		Mode 5 is enabled by setting bit 2 in <a href="#reg1">$01 - Mode Set Register 2</a>. Note
+		that this bit must be set before any Mode 5 specific registers can be set. Horizontal
+		resolution and interlace control are both set in <a href="#regC">$0C - Mode Set Register 4</a>.
+		When both bit 0 and 7 of that register are set to zero, a 32-column (256 pixel) wide display
+		is selected. When both are set to one, a 40-column (320 pixel) wide display is selected. Any
+		other combination of those two bits will result in a display mode with invalid timing and
+		should not be used.
+	</p>
+	<p>
+		Vertical resolution is controlled by a combination of the interlace control bits (bits 1 
+		and 2 of <a href="#regC">Register $0C</a>) and bit 3 of <a href="#reg1">$01 - Mode Set
+		Register 2</a>, which enables a 30 row (240 pixel) tall display when set. It's worth noting
+		that this bit does not change the number of actual lines sent to the display, but only how
+		many lines contain image data. Additional visible lines are filled with the border color.
+	<h3>Undocumented TMS9918A Modes</h3>
+	
+	<h2>Sprites</h2>
+	<h3>TMS9918A Modes</h3>
+	<h3>Mode 4</h3>
+	<h3>Mode 5</h3>
+	<h2>Registers</h2>
+	<table>
+		<tr>
+			<th>Number</th>
+			<th>Function</th>
+		</tr>
+		<tr>
+			<td><a href="#reg0">$00</a></td>
+			<td>Mode Set 1</td>
+		</tr>
+		<tr>
+			<td><a href="#reg1">$01</a></td>
+			<td>Mode Set 2</td>
+		</tr>
+		<tr>
+			<td><a href="#reg2">$02</a></td>
+			<td>Name Table Address/Scroll A Table Address</td>
+		</tr>
+		<tr>
+			<td><a href="#reg3">$03</a></td>
+			<td>Color Table Address/Window Table Address</td>
+		</tr>
+		<tr>
+			<td><a href="#reg4">$04</a></td>
+			<td>Pattern Generator Address/Scroll B Table Address</td>
+		</tr>
+	</table>
+	<h3 id="reg0">Register 0 - Mode Set 1</h3>
+	<table>
+		<tr>
+			<th>Bit</th>
+			<th>TMS9918A</th>
+			<th>SMS</th>
+			<th>Game Gear</th>
+			<th>Genesis Mode 4</th>
+			<th>Genesis Mode 5</th>
+		</tr>
+		<tr>
+			<td>7</td>
+			<td>None</td>
+			<td colspan="3">VScroll Lock</td>
+			<td>None</td>
+		</tr>
+		<tr>
+			<td>6</td>
+			<td>None</td>
+			<td>HScroll Lock</td>
+			<td>HScroll Lock<a href="#reg0_note_hslock">[1]</a></td>
+			<td>HScroll Lock</td>
+			<td>None</td>
+		</tr>
+		<tr>
+			<td>5</td>
+			<td>None</td>
+			<td>Col 0 Mask</td>
+			<td>None</td>
+			<td>Col 0 Mask</td>
+			<td>None</td>
+		</tr>
+		<tr>
+			<td>4</td>
+			<td>None</td>
+			<td colspan="4">HInt Enable</td>
+		</tr>
+		<tr>
+			<td>3</td>
+			<td>None</td>
+			<td colspan="3">Sprite Left Shift 8px</td>
+			<td>1=Invalid?</td>
+		</tr>
+		<tr>
+			<td>2</td>
+			<td>None</td>
+			<td colspan="3">Mode 4 Enable</td>
+			<td>Palette Select<a href="#reg0_node_pselect">[2]</a></td>
+		</tr>
+		<tr>
+			<td>1</td>
+			<td colspan="3">M2<a href="#reg0_m2">[3]</a></td>
+			<td>???</td>
+			<td>HVC Latch Enable</td>
+		</tr>
+		<tr>
+			<td>0</td>
+			<td colspan="5">External Sync</td>
+		</tr>
+	</table>
+	<p id="reg0_note_hslock">[1] Only in SMS mode, this bit does nothing in Game Gear mode</p>
+	<p id="reg0_node_pselect">[2] Normally set to 1. Only LSB of each color component in CRAM is used when 0.</p>
+	<p id="reg0_m2">[3] Middle bit of TMS9918 mode number when Mode 4 is disabled. Enables screen height control in Mode 4 on the SMS 2 and Game Gear.</p>
+	<h3 id="reg1">Register 1 - Mode Set 2</h3>
+	<table>
+		<tr>
+			<th>Bit</th>
+			<th>TMS9918A</th>
+			<th>SMS</th>
+			<th>Game Gear</th>
+			<th>Genesis Mode 4</th>
+			<th>Genesis Mode 5</th>
+		</tr>
+
+		<tr>
+			<td>7</td>
+			<td>16KB VRAM Mode</td>
+			<td colspan="3">None</td>
+			<td>128KB VRAM Mode</td>
+		</tr>
+		<tr>
+			<td>6</td>
+			<td colspan="5">Display Enable</td>
+		</tr>
+		<tr>
+			<td>5</td>
+			<td colspan="5">VInt Enable</td>
+		</tr>
+		<tr>
+			<td>4</td>
+			<td colspan="3">M1[1]</td>
+			<td>None</td>
+			<td>DMA Enable[2]</td>
+		</tr>
+		<tr>
+			<td>3</td>
+			<td colspan="3">M3[3]</td>
+			<td>???</td>
+			<td>240 Line Select[4]</td>
+		</tr>
+		<tr>
+			<td>2</td>
+			<td colspan="3">None</td>
+			<td>0 - Mode 5 select</td>
+			<td>1 - Mode 5 select</td>
+		</tr>
+		<tr>
+			<td>1</td>
+			<td colspan="4">Sprite Size Select[5]</td>
+			<td>None</td>
+		</tr>
+		<tr>
+			<td>0</td>
+			<td colspan="3">Sprite Zoom Enable</td>
+			<td>None</td>
+			<td>Weird Stuff<a href="#reg1_note_weird">[6]</a></td>
+		</tr>
+	</table>
+	<p id="reg1_note_m1">[1] LSB of TMS9918A Mode, selects 224 line display in Mode 4 on SMS2 and GG if M2 is set</p>
+	<p id="reg1_note_dma">[2] Doesn't actually enable DMA, but instead enables changing CD5 which is used to trigger a DMA operation</p>
+	<p id="reg1_note_m3">[3] MSB of TMS9918A Mode, selects 240 line display in Mode 4 on SMS2 and GG if M2 is set. Not valid in combination with M1 in Mode 4. 240 line display only valid in PAL regions.</p>
+	<p id="reg1_note_240">[4] Not valid in NTSC regions. Will result in a 255 line display with no vsync and no vertical interrupt.</p>
+	<p id="reg1_note_sprite_size">[5] 1 selects 16x16 in TMS9918A modes and 8x16 in Mode 4. 0 Selects 8x8 in both.</p>
+	<p id="reg1_note_weird">[6] According to Charles MacDonald, setting this bit in mode 5 causes the hscroll value to modify when HSync happens</p>
+	<h3 id="reg2">Register 2 - Name Table Address/Scroll A Table Address</h3>
+	<table>
+		<tr>
+			<th>Bits</th>
+			<th>TMS9918A</th>
+			<th>SMS</th>
+			<th>Game Gear</th>
+			<th>Genesis Mode 4</th>
+			<th>Genesis Mode 5</th>
+		</tr>
+		<tr>
+			<td>7</td>
+			<td colspan="5">None</td>
+		</tr>
+		<tr>
+			<td>6</td>
+			<td colspan="4">None</td>
+			<td>Bit 16 of Table A<a href="#reg2_note_p16">[1]</a></td>
+		</tr>
+		<tr>
+			<td>5-4</td>
+			<td colspan="4">None</td>
+			<td>Bit 15-14 of Table A</td>
+		</tr>
+		<tr>
+			<td>3</td>
+			<td colspan="4">Bit 13 of table address</td>
+			<td>Bit 13 of table A</td>
+		</tr>
+		<tr>
+			<td>2</td>
+			<td colspan="4">Bit 12 of table address</td>
+			<td>None</td>
+		</tr>
+		<tr>
+			<td>1</td>
+			<td>Bit 11 of table address</td>
+			<td colspan="2">Bit 11 of table address<a href="#reg2_note_lowbits_mode4">[2]</a></td>
+			<td>Bit 11 of table address</td>
+			<td>None</td>
+		</tr>
+		<tr>
+			<td>0</td>
+			<td>Bit 10 of table address</td>
+			<td>Bit 10 of table address<a href="#reg2_note_p10">[3]</a><a href="#reg2_note_p10_sms">[4]</a></td>
+			<td>Bit 10 of table address<a href="#reg2_note_p10">[3]</a></td>
+			<td>None</td>
+			<td>None</td>
+		</tr>
+	</table>
+	<p id="reg2_note_p16">[1] Only used when in 128KB VRAM mode. No function otherwise.
+	<p id="reg2_note_lowbits_mode4">[2] On the SMS2 and Game Gear these bits have no function in 224 and 240 line modes</p>
+	<p id="reg2_note_p10">[3] Only valid in TMS9918A modes.</p>
+	<p id="reg2_note_p10_sms">[4] On the SMS 1, this bit is anded with the MSB of the row number in name table fecthes in Mode 4. This bug was exploited by Y's and it will not render correctly on later systems as a result.</p> 
+	<h3 id="reg3">Register 3 - Color Table Address/Window Table Address</h3>
+	<table>
+		<tr>
+			<th>Bits</th>
+			<th>TMS9918A</th>
+			<th>SMS</th>
+			<th>Game Gear</th>
+			<th>Genesis Mode 4</th>
+			<th>Genesis Mode 5</th>
+		</tr>
+		<tr>
+			<td>7</td>
+			<td colspan="3">Color Table bit 13 <a href="#reg3_note_ct">[1]</a></td>
+			<td colspan="2">None</td>
+		</tr>
+		<tr>
+			<td>6</td>
+			<td colspan="3">Color Table bit 12 <a href="#reg3_note_ct">[1]</a></td>
+			<td>None</td>
+			<td>Window Table Bit 16 <a href="#reg3_note_wt16">[2]</a></td>
+		</tr>
+		<tr>
+			<td>5-2</td>
+			<td colspan="3">Color Table Bit 11-8 <a href="#reg3_note_ct">[1]</a></td>
+			<td>None</td>
+			<td>Window Table Bit 15-12</td>
+		</tr>
+		<tr>
+			<td>1</td>
+			<td colspan="3">Color Table Bit 7 <a href="#reg3_note_ct">[1]</a></td>
+			<td>None</td>
+			<td>Window Table Bit 11 <a href="#reg3_note_wt11">[3]</a></td>
+		</tr>
+		<tr>
+			<td>1</td>
+			<td colspan="3">Color Table Bit 6 <a href="#reg3_note_ct">[1]</a></td>
+			<td colspan="2">None</td>
+		</tr>
+	</table>
+	<p id="reg3_note_ct">[1] Color Table only used in some TMS9918A modes and not at all in Mode 4. Should be set to all ones on the SMS in Mode 4 to avoid issues with unintended masking.</p>
+	<p id="reg3_note_wt16">[2] Only used in 128KB VRAM mode</p>
+	<p id="reg3_note_wt11">[3] Only used in H32 mode</p>
+	<h3 id="reg4">Register 4 - Pattern Generator Address/Scroll B Table Address</h3>
+	<table>
+		<tr>
+			<th>Bits</th>
+			<th>TMS9918A</th>
+			<th>SMS</th>
+			<th>Game Gear</th>
+			<th>Genesis Mode 4</th>
+			<th>Genesis Mode 5</th>
+		</tr>
+		<tr>
+			<td>7-4</td>
+			<td colspan="5">None</td>
+		</tr>
+		<tr>
+			<td>3</td>
+			<td colspan="4">None</td>
+			<td>Scroll B Bit 16 <a href="#reg4_note_sb16">[1]</a>
+		</tr>
+		<tr>
+			<td>2-0</td>
+			<td colspan="3">Pattern Generator Bits 13-11 <a href="#reg4_note_pg">[2]</a></td>
+			<td>None</td>
+			<td>Scroll B Bit 15-13</td>
+		</tr>
+	</table>
+	<p id="reg4_note_sb16">[1] Only used in 128KB VRAM mode</p>
+	<p id="reg4_note_pg">[2] Only used in TMS9918A modes. Should be set to 1 on SMS 1 in Mode 4 to avoid unintended masking.</p>
+	<h3 id="reg5">Register 5 - Sprite Attribute Table Address</h3>
+	<table>
+		<tr>
+			<th>Bits</th>
+			<th>TMS9918A</th>
+			<th>SMS</th>
+			<th>Game Gear</th>
+			<th>Genesis Mode 4</th>
+			<th>Genesis Mode 5</th>
+		</tr>
+		<tr>
+			<td>7</td>
+			<td colspan="4">None</td>
+			<td>SAT Bit 16 <a href="#reg5_note_sat16">[1]</a></td>
+		</tr>
+		<tr>
+			<td>6-1</td>
+			<td colspan="4">SAT Bits 13-8</td>
+			<td>SAT Bit 15-10</td>
+		</tr>
+		<tr>
+			<td>0</td>
+			<td colspan="3">SAT Bit 7 <a href="#reg5_note_sat7">[2]</a></td>
+			<td>None</td>
+			<td>SAT Bit 9 <a herf="#reg5_note_sat8">[3]</a></td>
+		</tr>
+	</table>
+	<p id="reg5_note_sat16">[1] Only used in 128KB VRAM mode</p>
+	<p id="reg5_note_sat7">[2] Only valid in TMS9918A modes. Will cause X/Pattern loads to take place from bottom half of table when cleared on SMS 1 in Mode 4.</p>
+	<p id="reg5_note_sat8">[3] Only used in H32 mode</p>
+	<h3 id="reg6">Register 6 - Sprite Tile Base</h3>
+	<table>
+		<tr>
+			<th>Bits</th>
+			<th>TMS9918A</th>
+			<th>SMS</th>
+			<th>Game Gear</th>
+			<th>Genesis Mode 4</th>
+			<th>Genesis Mode 5</th>
+		</tr>
+		<tr>
+			<td>7-6</td>
+			<td colspan="5">None</td>
+		</tr>
+		<tr>
+			<td>5</td>
+			<td colspan="4">None</td>
+			<td>Tile Address Bit 16 <a href="#reg6_ta16">[1]</a></td>
+		</tr>
+		<tr>
+			<td>4-3</td>
+			<td colspan="5">None</td>
+		</tr>
+		<tr>
+			<td>2</td>
+			<td colspan="4">Tile Address Bit 13</td>
+			<td>None</td>
+		</tr>
+		<tr>
+			<td>1-0</td>
+			<td colspan="3">Tile Address Bit 12-11 <a href="#reg6_ta12_11">[2]</a></td>
+			<td colspan="2">None</td>
+		</tr>
+	</table>
+	<p id="reg6_ta16">[1] Only used in 128KB VRAM mode</p>
+	<p id="reg6_ta12_11">[2] Only valid in TMS9918A modes. Will cause masking of relevant bits of tile addresses if cleared on the SMS 1 in Mode 4.</p>
+	<h3 id="reg7">Register 7 - Text/Background Color</h3>
+	<table>
+		<tr>
+			<th>Bits</th>
+			<th>TMS9918A</th>
+			<th>SMS</th>
+			<th>Game Gear</th>
+			<th>Genesis Mode 4</th>
+			<th>Genesis Mode 5</th>
+		</tr>
+		<tr>
+			<td>7-6</td>
+			<td colspan="3">Text Color Bit 3-2 <a href="#reg7_tc">[1]</a></td>
+			<td colspan="2">None</td>
+		</tr>
+		<tr>
+			<td>5-4</td>
+			<td colspan="3">Text Color Bit 1-0 <a href="#reg7_tc">[1]</a></td>
+			<td>None</td>
+			<td>Background Color Palette Index</td>
+		</tr>
+		<tr>
+			<td>3-0</td>
+			<td colspan="5">Background Color <a href="#reg7_bgc">[2]</a></td>
+		</tr>
+	</table>
+	<p id="reg7_tc">[1] Only used in TMS9918A modes.</p>
+	<p id="reg7_bgc">[2] An index into a fixed palette in TMS9918A modes, the sprite palette in Mode 4 and the selected palette in Mode 5</p>
+	<h3 id="reg8">Register 8 - Background X Scroll (Mode 4 only)</h3>
+	<table>
+		<tr>
+			<th>Bits</th>
+			<th>SMS</th>
+			<th>Game Gear</th>
+			<th>Genesis Mode 4</th>
+			<th>Genesis Mode 5</th>
+		</tr>
+		<tr>
+			<td>7-0</td>
+			<td colspan="3">X Scroll Value</td>
+			<td>None</td>
+		</tr>
+	</table>
+	<h3 id="reg9">Register 9 - Background Y Scroll (Mode 4 only)</h3>
+	<table>
+		<tr>
+			<th>Bits</th>
+			<th>SMS</th>
+			<th>Game Gear</th>
+			<th>Genesis Mode 4</th>
+			<th>Genesis Mode 5</th>
+		</tr>
+		<tr>
+			<td>7-0</td>
+			<td colspan="3">Y Scroll Value</td>
+			<td>None</td>
+		</tr>
+	</table>
+	<h3 id="regA">Register A - Horizotal Interrupt Counter (Mode 4 & 5 only)</h3>
+	<table>
+		<tr>
+			<th>Bits</th>
+			<th>SMS</th>
+			<th>Game Gear</th>
+			<th>Genesis Mode 4</th>
+			<th>Genesis Mode 5</th>
+		</tr>
+		<tr>
+			<td>7-0</td>
+			<td colspan="5">Number of lines before HInt fires</td>
+		</tr>
+	</table>
+	<h3 id="regB">Register B - Mode Set 3 (Mode 5 only)</h3>
+	<table>
+		<tr>
+			<th>Bits</th>
+			<th>Function</th>
+		</tr>
+		<tr>
+			<td>7-4</td>
+			<td>None</td>
+		</tr>
+		<tr>
+			<td>3</td>
+			<td>External Interrupt Enable</td>
+		</tr>
+		<tr>
+			<td>2</td>
+			<td>2 Column Vertical Scroll Enable</td>
+		</tr>
+		<tr>
+			<td>1</td>
+			<td>Horizontal Scroll Table Bits 9-5 Enable</td>
+		</tr>
+		<tr>
+			<td>0</td>
+			<td>Horizontal Scroll Table Bits 4-2 Enable</td>
+		</tr>
+	</table>
+	<h3 id="regC">Register C - Mode Set 4 (Mode 5 only)</h3>
+	<table>
+		<tr>
+			<th>Bits</th>
+			<th>Function</th>
+		</tr>
+		<tr>
+			<td>7</td>
+			<td>RS0 - H40 Enable <a href="#regc_note_h40">[1]</a></td>
+		</tr>
+		<tr>
+			<td>6</td>
+			<td>VSY - Replace VSync Output with Pixel Clock</td>
+		</tr>
+		<tr>
+			<td>5</td>
+			<td>HSY - Something involving HSync apparently</td>
+		</tr>
+		<tr>
+			<td>4</td>
+			<td>SPR - External Pixel Bus Enable</td>
+		</tr>
+		<tr>
+			<td>3</td>
+			<td>SHI - Shadow/Highlight Mode Enable</td>
+		</tr>
+		<tr>
+			<td>2</td>
+			<td>LSM1 - Double Resolution Enable <a href="#regc_note_doubleres">[2]</a></td>
+		</tr>
+		<tr>
+			<td>1</td>
+			<td>LSM0 - Interlace Enable</td>
+		</tr>
+		<tr>
+			<td>0</td>
+			<td>RS1 - External Clock Enable <a href="#regc_note_h40">[1]</a></td>
+		</tr>
+	</table>
+	<p id="regc_note_h40">
+		[1] RS0 enables a 320 pixel wide display and changes the internal clock source to MCLK/4. 
+		RS1 switches to the external clock source which is mostly MCLK/4, but switches to MCLK/5 for parts of HSync to get the line duration to match the H32 duration.
+		Normally RS0 and RS1 should be set to the same value as other combinations result in timings that are further out of spec than normal, but with a flexible enough display other combinations are possible.
+		The full list of modes are as follows on an NTSC system:
+	</p>
+	<table>
+		<tr>
+			<th>RS1</th>
+			<th>RS0</th>
+			<th>Width</th>
+			<th>Horizontal Rate</th>
+			<th>Vertical Rate</th>
+		</tr>
+		<tr>
+			<td>0</td>
+			<td>0</td>
+			<td>256</td>
+			<td>15.7 kHz</td>
+			<td>59.92 Hz</td>
+		</tr>
+		<tr>
+			<td>0</td>
+			<td>1</td>
+			<td>320</td>
+			<td>15.98 kHz</td>
+			<td>60.99 Hz</td>
+		</tr>
+		<tr>
+			<td>1</td>
+			<td>0</td>
+			<td>256</td>
+			<td>19.62 kHz</td>
+			<td>74.90 Hz</td>
+		</tr>
+		<tr>
+			<td>1</td>
+			<td>1</td>
+			<td>320</td>
+			<td>15.7 kHz</td>
+			<td>59.92 Hz</td>
+		</tr>
+	</table>
+	<p>On a PAL system, they are as follows:</p>
+	<table>
+		<tr>
+			<th>RS1</th>
+			<th>RS0</th>
+			<th>Width</th>
+			<th>Horizontal Rate</th>
+			<th>Vertical Rate</th>
+		</tr>
+		<tr>
+			<td>0</td>
+			<td>0</td>
+			<td>256</td>
+			<td>15.56 kHz</td>
+			<td>49.86 Hz</td>
+		</tr>
+		<tr>
+			<td>0</td>
+			<td>1</td>
+			<td>320</td>
+			<td>15.83 kHz</td>
+			<td>50.75 Hz</td>
+		</tr>
+		<tr>
+			<td>1</td>
+			<td>0</td>
+			<td>256</td>
+			<td>19.45 kHz</td>
+			<td>62.33 Hz</td>
+		</tr>
+		<tr>
+			<td>1</td>
+			<td>1</td>
+			<td>320</td>
+			<td>15.56 kHz</td>
+			<td>49.86 Hz</td>
+		</tr>
+	</table>
+	<p id="regc_note_doubleres">[2] Should only be set along with LSM0. Unclear what happens if set by itself.</p>
+	<h3 id="regD">Register D - Horizontal Scroll Table Address (Mode 5 only)</h3>
+	<table>
+		<tr>
+			<th>Bits</th>
+			<th>Function</th>
+		</tr>
+		<tr>
+			<td>7</td>
+			<td>None</td>
+		</tr>
+		<tr>
+			<td>6</td>
+			<td>Table Address Bit 16 <a href="#regd_note_ta16">[1]</a></td>
+		</tr>
+		<tr>
+			<td>5-0</td>
+			<td>Table Address Bit 15-10</td>
+		</tr>
+	</table>
+	<p id="regd_note_ta16">[1] Only used in 128KB VRAM Mode</p>
+	<h3 id="regE">Regsiter E - Background Tile Base Address (Mode 5 only)</h3>
+	<table>
+		<tr>
+			<th>Bits</th>
+			<th>Function</th>
+		</tr>
+		<tr>
+			<td>7-5</td>
+			<td>None</td>
+		</tr>
+		<tr>
+			<td>4</td>
+			<td>Scroll B Tile Address Bit 16 <a href="#rege_note_bit16">[1]</a></td>
+		</tr>
+		<tr>
+			<td>3-1</td>
+			<td>None</td>
+		</tr>
+		<tr>
+			<td>0</td>
+			<td>Scroll A Tile Address Bit 16 <a href="#rege_note_bit16">[1]</a></td>
+		</tr>
+	</table>
+	<p id="rege_note_bit16">[1] Only used in 128KB VRAM Mode</p>
+	<h3 id="regF">Register F - Auto Increment (Mode 5 only)</h3>
+	<table>
+		<tr>
+			<th>Bits</th>
+			<th>Function</th>
+		</tr>
+		<tr>
+			<td>7-0</td>
+			<td>Value added to address register after each operation</td>
+		</tr>
+	</table>
+	<h2>VRAM Interface</h2>
+	
+	<h3>Genesis Mode 5 Address Bit Mapping - 64KB Mode</h3>
+	<table>
+		<tr>
+			<th>DRAM Bit (R=row,C=col)</th>
+			<th>Logical Bit</th>
+		</tr>
+		<tr>
+			<td>R7</td>
+			<td>A9</td>
+		</tr>
+		<tr>
+			<td>R6</td>
+			<td>A8</td>
+		</tr>
+		<tr>
+			<td>R5</td>
+			<td>A7</td>
+		</tr>
+		<tr>
+			<td>R4</td>
+			<td>A6</td>
+		</tr>
+		<tr>
+			<td>R3</td>
+			<td>A5</td>
+		</tr>
+		<tr>
+			<td>R2</td>
+			<td>A4</td>
+		</tr>
+		<tr>
+			<td>R1</td>
+			<td>A3</td>
+		</tr>
+		<tr>
+			<td>R0</td>
+			<td>A2</td>
+		</tr>
+		<tr>
+			<td>C7</td>
+			<td>A15</td>
+		</tr>
+		<tr>
+			<td>C6</td>
+			<td>A14</td>
+		</tr>
+		<tr>
+			<td>C5</td>
+			<td>A13</td>
+		</tr>
+		<tr>
+			<td>C4</td>
+			<td>A12</td>
+		</tr>
+		<tr>
+			<td>C3</td>
+			<td>A11</td>
+		</tr>
+		<tr>
+			<td>C2</td>
+			<td>A10</td>
+		</tr>
+		<tr>
+			<td>C1</td>
+			<td>A1</td>
+		</tr>
+		<tr>
+			<td>C0</td>
+			<td>A0</td>
+		</tr>
+	</table>
+	
+	
+	<h3>Genesis Mode 4 Address Bit Mapping</h3>
+	<table>
+		<tr>
+			<th>DRAM Bit (R=row,C=col)</th>
+			<th>Logical Bit</th>
+		</tr>
+		<tr>
+			<td>R7</td>
+			<td>A8</td>
+		</tr>
+		<tr>
+			<td>R6</td>
+			<td>A7</td>
+		</tr>
+		<tr>
+			<td>R5</td>
+			<td>A6</td>
+		</tr>
+		<tr>
+			<td>R4</td>
+			<td>A5</td>
+		</tr>
+		<tr>
+			<td>R3</td>
+			<td>A4</td>
+		</tr>
+		<tr>
+			<td>R2</td>
+			<td>A3</td>
+		</tr>
+		<tr>
+			<td>R1</td>
+			<td>A2</td>
+		</tr>
+		<tr>
+			<td>R0</td>
+			<td>A1</td>
+		</tr>
+		<tr>
+			<td>C7</td>
+			<td>0</td>
+		</tr>
+		<tr>
+			<td>C6</td>
+			<td>0</td>
+		</tr>
+		<tr>
+			<td>C5</td>
+			<td>A13</td>
+		</tr>
+		<tr>
+			<td>C4</td>
+			<td>A12</td>
+		</tr>
+		<tr>
+			<td>C3</td>
+			<td>A11</td>
+		</tr>
+		<tr>
+			<td>C2</td>
+			<td>A10</td>
+		</tr>
+		<tr>
+			<td>C1</td>
+			<td>A9</td>
+		</tr>
+		<tr>
+			<td>C0</td>
+			<td>A0</td>
+		</tr>
+	</table>
+</body>
+</html>
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