Mercurial > repos > simple16

annotate simple_console.txt @ 40:413e7b9c0db1

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Added flag change documentation for all instructions. Added hyperlinks to individual instructions. Added overviews for all the peripherals
author Michael Pavone <pavone@retrodev.com>
date Thu, 07 Apr 2016 21:58:27 -0700
parents 351a0d0cce3b
children 6e7bfe83d2b0
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
0
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1 Key:
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2 1 = literal 1 bit
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
3 0 = literal 0 bit
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
4 O = opcode bit
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
5 D = destination register bit
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
6 A = source A register bit
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
7 B = source B register bit
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
8
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
9 DDDD AAAA BBBB OOOO
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
10
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
11 0: ldim
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
12 D = destination reg
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
13 A and B form 8-bit immediate value
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
14 1: ldimh
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
15 D = destination reg
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
16 A and B form 8-bit immediate value
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
17 2: ld8
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
18 3: ld16
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
19 4: str8
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
20 5: str16
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
21 6: add
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
22 7: adc
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
23 8: and
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
24 9: or
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
25 A: xor
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
26 B: lsl
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
27 C: lsr
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
28 D: asr
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
29 E: bcc
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
30 F: single source
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
31
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
32
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
33
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
34 DDDD AAAA OOOO 1111
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
35
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
36 single source
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
37
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
38 0: mov
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
39 1: neg
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
40 2: not
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
41 3: cmp
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
42 4: call
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
43 A = register containing pointer to function
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
44 D = register that will store PC value
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
45 5: swap
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
46 6: in
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
47 7: out
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
48 8: ini
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
49 9: outi
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
50 A: addi
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
51 B: andi
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
52 C: ori
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
53 D: ls[lr]i
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
54 MSB of AAAA determines direction
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
55 LS 3 bits determines magnitude
2
6204c81e2933 Revert changes to handling of immediate versions of bitwise instructions. Replace asri with cmpi.
Michael Pavone <pavone@retrodev.com>
parents: 0
diff changeset
56 E: cmpi
0
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
57 F: single reg
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
58
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
59
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
60 DDDD OOOO 1111 1111
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
61
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
62 0: reti - return from interrupt, D = register to restore from uer
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
63 1: trap
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
64 2: trapi
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
65 3: getepc
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
66 4: setepc
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
67 5: getesr
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
68 6: setesr
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
69 7: getenum
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
70 8: setenum
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
71 9: getuer
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
72 A: setuer
5
18b66690ae13 Removed redundant definitino of some exception register instructinos in spec
Michael Pavone <pavone@retrodev.com>
parents: 4
diff changeset
73 B: invalid
18b66690ae13 Removed redundant definitino of some exception register instructinos in spec
Michael Pavone <pavone@retrodev.com>
parents: 4
diff changeset
74 C: invalid
18b66690ae13 Removed redundant definitino of some exception register instructinos in spec
Michael Pavone <pavone@retrodev.com>
parents: 4
diff changeset
75 D: invalid
0
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
76 E: invalid
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
77 F: invalid
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
78
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
79
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
80 Registers:
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
81
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
82 r0 - r12 : general purpose
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
83 r13 : technically general purpose, but canonically the stack register
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
84 r14 : PC
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
85 r15 : status register
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
86
3
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
87 Special Registers
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
88 epc - Exception PC - Stores PC value to resume to when entering an exception handler
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
89 esr - Exception SR - same as above, but for SR
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
90 eur - Exceptuion User Reg - reg for temporary storage of a reg in a handler, intended to be used for the stack pointer
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
91 enum - Exception Number - holds the number of the most recent exception
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
92
0
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
93 IO: Ports
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
94
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
95 0: Controller 1
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
96 1: Controller 2
27
351a0d0cce3b Updated spec to make the 3rd and 4th controller IO ports as reserved
Michael Pavone <pavone@retrodev.com>
parents: 25
diff changeset
97 2: Reserved
351a0d0cce3b Updated spec to make the 3rd and 4th controller IO ports as reserved
Michael Pavone <pavone@retrodev.com>
parents: 25
diff changeset
98 3: Reserved
0
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
99
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
100 4: Channel A Freq
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
101 Load value for a 16-bit down-counter
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
102 Polarity of output is switched on transition from 1 to 0
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
103 Value is loaded on cycles where counter is 0
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
104 Special case value of 0 in this register forces polarity to positive
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
105 5: Channel B Freq
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
106 6: Channel C Freq
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
107 7: Channel D Freq
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
108
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
109 8: Channel A/B Vol
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
110 9: Channel C/D Vol
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
111
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
112 A: Timer Freq
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
113 B: "Serial" Debug Port
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
114
3
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
115 C: Write Vertical Scroll : Read Vertical Position
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
116 MMMM MCCC CCCC CFFF
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
117 C = coarse scroll bit
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
118 F = fine scroll bit
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
119 M = mask bit
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
120 controls which bits come directly from register
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
121 and which bits come from the sum of the register
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
122 and the current line number
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
123
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
124 D: Write Horizontal Scroll : Read Horizontal Position
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
125 xxxx xxxC CCCC CFFF
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
126 C = coarse scroll bit
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
127 F = fine scroll bit
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
128 x = unused
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
129 E: Write Dest Address : Read Status
4
8170d60f188b Added basic rendering timing outline and made some other minor spec changes
Michael Pavone <pavone@retrodev.com>
parents: 3
diff changeset
130 F: Write Data : Read ???
3
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
131
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
132
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
133 Name Table Start Address:
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
134 0VVV VVVV VHHH HHH0
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
135
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
136 V = Coarse scroll bit from vertical scroll value
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
137 H = Coarse scroll bit from horizontal scroll value
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
138
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
139 VDP Memory Map
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
140 0000 - 7FFF = Pattern/Name Table RAM
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
141 8000 - FDFF = unused, returns $FFFF
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
142 FE00 - FEFF = Sprite RAM
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
143 FF00 - FF7F = Palette RAM
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
144 FF80 - FFFF = Palette RAM (mirror)
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
145
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
146 Another View -
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
147 MSB determines whether destination is main RAM
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
148 For MSB 1
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
149 Next 7 MSB determines which special RAM is the destination
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
150 Only values of 7E and 7F are valid for these bits at present
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
151 8 LSB determine offset (1 LSB ignored)
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
152
4
8170d60f188b Added basic rendering timing outline and made some other minor spec changes
Michael Pavone <pavone@retrodev.com>
parents: 3
diff changeset
153 Writing to Data port puts value into a one word FIFO
3
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
154 Offset within memory type is increment when word is pulled from FIFO
4
8170d60f188b Added basic rendering timing outline and made some other minor spec changes
Michael Pavone <pavone@retrodev.com>
parents: 3
diff changeset
155 Writing to the FIFO when it is full will cause the existing entry to be overwritten
8170d60f188b Added basic rendering timing outline and made some other minor spec changes
Michael Pavone <pavone@retrodev.com>
parents: 3
diff changeset
156
3
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
157
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
158 Pattern Format:
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
159 4bpp in an 8x8 tile arrangement
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
160
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
161
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
162 Sprite Table Entry:
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
163
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
164 XXXXXXXX YYYYYYYY
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
165 IXPVHSNN NNNNNNNN
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
166
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
167 S: size -- 0 = 8x8, 1 = 16x16
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
168 P: Palette selector
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
169 H: Horizontal flip
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
170 V: Vertical flip
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
171 I: Priority
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
172 N: Name
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
173 X: X position (left of screen = 16, right of screen = ?)
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
174 Y: Y position (top of screen = 16, bottom of screen = 240)
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
175
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
176
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
177 Name Table Entry:
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
178
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
179 IPPVHxNN NNNNNNNN
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
180
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
181 P: Palette selector
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
182 H: Horizontal flip
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
183 V: Vertical flip
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
184 I: Priority
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
185 N: Name
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
186 x: Unused, should be set to 0
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
187
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
188 26.112 MHZ Clock
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
189 Dot Clock Divider 4
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
190 CPU Clock Divider 20 (assuming 1 cycle/instruction, 5 for 4 cycles/instruction)
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
191 Audio Timer Divider 34
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
192 Audio Output Divider 544
25
fb14515266f4 Implemented timer and timer interrupts. Added get/setvbr instructions. Fixed assembler bug. Moved mnemonics into a separate source file
Michael Pavone <pavone@retrodev.com>
parents: 5
diff changeset
193 Interrupt Timer Divider 32
3
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
194
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
195 Alternatively 13.056 Mhz clock and cut the dividers in half
0
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
196
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
197
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
198
3
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
199 H-Counter goes from 0-415 and then wraps back to zero
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
200 V-Counter goes from 0-261 and then wraps back to zero
08b69e3f9f17 Fleshed out the video hardware design somewhat
Michael Pavone <pavone@retrodev.com>
parents: 2
diff changeset
201 V-Counter increments when H-Counter wraps
4
8170d60f188b Added basic rendering timing outline and made some other minor spec changes
Michael Pavone <pavone@retrodev.com>
parents: 3
diff changeset
202
8170d60f188b Added basic rendering timing outline and made some other minor spec changes
Michael Pavone <pavone@retrodev.com>
parents: 3
diff changeset
203 Rendering Process:
8170d60f188b Added basic rendering timing outline and made some other minor spec changes
Michael Pavone <pavone@retrodev.com>
parents: 3
diff changeset
204 208 main VRAM access slots
8170d60f188b Added basic rendering timing outline and made some other minor spec changes
Michael Pavone <pavone@retrodev.com>
parents: 3
diff changeset
205 123 slots for background
8170d60f188b Added basic rendering timing outline and made some other minor spec changes
Michael Pavone <pavone@retrodev.com>
parents: 3
diff changeset
206 160-123 = 37 extra slots during active display
8170d60f188b Added basic rendering timing outline and made some other minor spec changes
Michael Pavone <pavone@retrodev.com>
parents: 3
diff changeset
207 48 slots during inactive display
8170d60f188b Added basic rendering timing outline and made some other minor spec changes
Michael Pavone <pavone@retrodev.com>
parents: 3
diff changeset
208 80 slots for sprite rendering
8170d60f188b Added basic rendering timing outline and made some other minor spec changes
Michael Pavone <pavone@retrodev.com>
parents: 3
diff changeset
209 5 slots remain for refresh or external access
8170d60f188b Added basic rendering timing outline and made some other minor spec changes
Michael Pavone <pavone@retrodev.com>
parents: 3
diff changeset
210
8170d60f188b Added basic rendering timing outline and made some other minor spec changes
Michael Pavone <pavone@retrodev.com>
parents: 3
diff changeset
211 Since sprite rendering needs to intrude on active display period,
8170d60f188b Added basic rendering timing outline and made some other minor spec changes
Michael Pavone <pavone@retrodev.com>
parents: 3
diff changeset
212 a double buffered line buffer is needed. Useful for VGA compatibility anyway
8170d60f188b Added basic rendering timing outline and made some other minor spec changes
Michael Pavone <pavone@retrodev.com>
parents: 3
diff changeset
213