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annotate simple_console.txt @ 43:6e7bfe83d2b0

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Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
author Michael Pavone <pavone@retrodev.com>
date Sat, 27 Aug 2016 22:38:31 -0700
parents 351a0d0cce3b
children 51672bd41cdd
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0
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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1 Key:
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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2 1 = literal 1 bit
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3 0 = literal 0 bit
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4 O = opcode bit
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5 D = destination register bit
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6 A = source A register bit
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7 B = source B register bit
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8
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9 DDDD AAAA BBBB OOOO
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10
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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11 0: ldim
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12 D = destination reg
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13 A and B form 8-bit immediate value
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14 1: ldimh
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15 D = destination reg
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16 A and B form 8-bit immediate value
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17 2: ld8
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18 3: ld16
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19 4: str8
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20 5: str16
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21 6: add
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22 7: adc
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23 8: and
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24 9: or
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25 A: xor
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26 B: lsl
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27 C: lsr
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28 D: asr
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29 E: bcc
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30 F: single source
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31
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32
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33
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34 DDDD AAAA OOOO 1111
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35
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36 single source
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37
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38 0: mov
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39 1: neg
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40 2: not
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41 3: cmp
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42 4: call
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43 A = register containing pointer to function
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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44 D = register that will store PC value
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45 5: swap
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6e7bfe83d2b0 Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
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46 6: longjmp
6e7bfe83d2b0 Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
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47 A = register containing pointer to function
6e7bfe83d2b0 Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
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48 D = register containing new code segment value
6e7bfe83d2b0 Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
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49 7: ini
6e7bfe83d2b0 Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
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50 8: outi
6e7bfe83d2b0 Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
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51 9: addi
6e7bfe83d2b0 Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
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52 A: andi
6e7bfe83d2b0 Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
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53 B: ori
6e7bfe83d2b0 Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
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54 C: xori
0
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55 D: ls[lr]i
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56 MSB of AAAA determines direction
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57 LS 3 bits determines magnitude
2
6204c81e2933 Revert changes to handling of immediate versions of bitwise instructions. Replace asri with cmpi.
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58 E: cmpi
0
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59 F: single reg
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60
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61
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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62 DDDD OOOO 1111 1111
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63
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64 0: reti - return from interrupt, D = register to restore from uer
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65 1: trapi
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66 2: getepc
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67 3: setepc
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68 4: getepch
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69 5: setepch
6e7bfe83d2b0 Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
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70 6: getesr
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71 7: setesr
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72 8: getenum
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73 9: setenum
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74 A: getuer
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75 B: setuer
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76 C: getvbr
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77 D: setvbr
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78 E: getdatabanks
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79 F: setdatabanks
0
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80
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81
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82 Registers:
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83
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84 r0 - r12 : general purpose
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85 r13 : technically general purpose, but canonically the stack register
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86 r14 : PC
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87 r15 : status register
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88
3
08b69e3f9f17 Fleshed out the video hardware design somewhat
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89 Special Registers
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90 epc - Exception PC - Stores PC value to resume to when entering an exception handler
43
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91 epch - High 7-bits of PC
3
08b69e3f9f17 Fleshed out the video hardware design somewhat
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92 esr - Exception SR - same as above, but for SR
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93 eur - Exceptuion User Reg - reg for temporary storage of a reg in a handler, intended to be used for the stack pointer
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94 enum - Exception Number - holds the number of the most recent exception
43
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95 databanks - Holds the upper bytes used for data accesses (MSB = byte for upper half of memory space, LSB = byte for lower half of memory space)
3
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96
0
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97 IO: Ports
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98
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99 0: Controller 1
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100 1: Controller 2
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351a0d0cce3b Updated spec to make the 3rd and 4th controller IO ports as reserved
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101 2: Reserved
351a0d0cce3b Updated spec to make the 3rd and 4th controller IO ports as reserved
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102 3: Reserved
0
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103
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104 4: Channel A Freq
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105 Load value for a 16-bit down-counter
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106 Polarity of output is switched on transition from 1 to 0
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107 Value is loaded on cycles where counter is 0
43
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108 Special case value of 0 in this register forces polarity to positive, useful for PCM playback
0
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109 5: Channel B Freq
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110 6: Channel C Freq
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111 7: Channel D Freq
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112
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113 8: Channel A/B Vol
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114 9: Channel C/D Vol
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115
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116 A: Timer Freq
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117 B: "Serial" Debug Port
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118
43
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119 C: Framebuffer start offset : Read Vertical Position
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120 D: Graphics mode : Read Horizontal Position
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121 EDVP PSSS SSEE EEEF
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122 E = 0 display disabled, 1 display enabled
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123 D = 0 4 bpp, 1 8bpp
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124 F = 0 front buffer is lower 64K, 1 front buffer is upper 64K
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125 P = palette select
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126 S = blanked lines at start of frame
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127 E = blanked lines at end of frame
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128 E: CRAM update port : Read Status
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129 1st write determines destination and length
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130 DDDD DDDD LLLL LLLL
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131 Next L writes are written to D and subsequent addresses
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132
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133 F: Reserved
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134
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135
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136 Video Hardware:
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137 128KB of VRAM organized into two 64KB linear framebuffers
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138 Pixels are 4bpp or 8bbp in chunky format
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139 256 words of 16-bit CRAM
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140 In 4bpp mode, P field of graphics mode selects one of 4, 16 color palettes
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141 S and E fields of mode allow hardware letter boxing, effectively increasing the length of vblank
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142 F field selects which 64KB framebuffer is used for the active display
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143 Active buffer is inaccessible to CPU, but CPU has free reign over inactive buffer
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144 H-Counter goes from 0-415 and then wraps back to zero
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145 V-Counter goes from 0-261 and then wraps back to zero
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146 V-Counter increments when H-Counter wraps
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147
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148 Memory Map
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149 23-bit address space
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150 $0 - $3FFFFF - ROM
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151 $400000 - $4FFFFF - 128K RAM, mirrored every 128KB
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152 $500000 - $6FFFFF - Reserved
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153 $700000 - $7FFFFF - 64KB VRAM back buffer, mirrored every 64KB
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154
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155
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156 26.112 MHZ Clock
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157 Dot Clock Divider 4
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158 CPU Clock Divider 4 (assuming 1 cycle/instruction, 1 for 4 cycles/instruction)
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159 Audio Timer Divider 34
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160 Audio Output Divider 544
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fb14515266f4 Implemented timer and timer interrupts. Added get/setvbr instructions. Fixed assembler bug. Moved mnemonics into a separate source file
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161 Interrupt Timer Divider 32
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162
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163 Alternatively 13.056 Mhz clock and cut the dividers in half
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7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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164
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165