Mercurial > repos > simple16
annotate src/cpu.h @ 43:6e7bfe83d2b0
Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
author | Michael Pavone <pavone@retrodev.com> |
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date | Sat, 27 Aug 2016 22:38:31 -0700 |
parents | fb14515266f4 |
children | 51672bd41cdd |
rev | line source |
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0
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Initial commit. CPU working well enough for simple hello world program.
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1 #ifndef CPU_H_ |
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2 #define CPU_H_ |
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3 |
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4 |
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5 typedef struct cpu cpu; |
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6 |
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7 typedef void (*port_write_fun) (cpu *context, uint8_t port, uint16_t value); |
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8 typedef uint16_t (*port_read_fun) (cpu *context, uint8_t port); |
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9 |
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10 typedef struct { |
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11 port_write_fun write; |
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12 port_read_fun read; |
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13 } port_handler; |
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14 |
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15 |
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16 #define MEM_READ 1 |
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17 #define MEM_WRITE 2 |
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18 |
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19 typedef struct { |
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20 uint8_t *base; |
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21 uint32_t start; |
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22 uint32_t end; |
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23 uint32_t mask; |
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24 uint8_t flags; |
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25 } memory_region; |
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26 |
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27 |
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28 struct cpu { |
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29 void *system; |
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30 uint32_t cycles; |
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31 uint32_t clock_inc; |
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32 uint32_t current_target; |
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33 uint32_t num_mem_regions; |
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34 uint16_t regs[16]; |
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35 uint16_t exception; |
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36 uint16_t exception_pc; |
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37 uint16_t exception_pch; |
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38 uint16_t exception_sr; |
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39 uint16_t exception_ur; |
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40 uint16_t vector_base; |
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41 uint32_t pc_msb; |
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42 uint32_t data_low_msb; |
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43 uint32_t data_high_msb; |
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44 |
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45 uint16_t prefetch; |
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46 |
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47 uint8_t state; |
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48 uint8_t pending_interrupts; |
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49 |
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50 port_handler port_handlers[16]; |
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51 memory_region mem_regions[]; |
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52 }; |
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53 |
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54 cpu* alloc_cpu(uint32_t clock_divider, uint32_t num_regions, memory_region *regions); |
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55 void run_cpu(cpu *context, uint32_t target_cycle); |
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56 //To be implemented by system |
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57 uint32_t next_interrupt_cycle(cpu *context, uint8_t mask); |
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58 uint8_t get_current_interrupts(cpu *context); |
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59 void ack_interrupt(cpu *context, int which); |
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60 |
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61 extern char * mnemonics[]; |
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62 extern char * mnemonics_single_src[]; |
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63 extern char * mnemonics_single_reg[]; |
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64 |
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65 enum { |
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66 LDIM, |
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67 LDIMH, |
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68 LD8, |
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69 LD16, |
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70 STR8, |
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71 STR16, |
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72 ADD, |
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73 ADC, |
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74 AND, |
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75 OR, |
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76 XOR, |
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77 LSL, |
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78 LSR, |
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79 ASR, |
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80 BCC, |
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81 SINGLE_SOURCE |
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82 }; |
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83 |
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84 enum { |
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85 MOVE, |
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86 NEG, |
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87 NOT, |
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88 CMP, |
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89 CALL, |
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90 SWAP, |
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91 LONGJMP, |
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92 INI, |
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93 OUTI, |
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94 ADDI, |
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95 ANDI, |
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96 ORI, |
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97 XORI, |
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98 LSI, |
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99 CMPI, |
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100 SINGLE_REG |
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101 }; |
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102 |
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103 enum { |
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104 RETI, |
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105 TRAPI, |
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106 GETEPC, |
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107 SETEPC, |
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108 GETEPCH, |
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109 SETEPCH, |
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110 GETESR, |
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111 SETESR, |
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112 GETEUR, |
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113 SETEUR, |
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114 GETENUM, |
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115 SETENUM, |
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116 GETVBR, |
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117 SETVBR, |
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118 GETDATABANKS, |
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119 SETDATABANKS, |
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120 }; |
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121 |
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122 enum { |
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123 COND_ALWAYS, |
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124 COND_NEVER, |
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125 COND_ZERO, |
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126 COND_NZERO, |
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127 COND_NEG, |
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128 COND_POS, |
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129 COND_CARRY, |
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130 COND_NCARRY, |
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131 COND_GREATER, |
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132 COND_LEQ |
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133 }; |
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134 |
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135 #define REG_PC 14 |
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136 #define REG_SR 15 |
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137 |
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138 #endif //CPU_H_ |