Mercurial > repos > simple16
annotate simple16.html @ 42:a64e11e48a41
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| author | Michael Pavone <pavone@retrodev.com> |
|---|---|
| date | Mon, 11 Apr 2016 23:35:51 -0700 |
| parents | 413e7b9c0db1 |
| children | 5338b9affd09 |
| rev | line source |
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| 39 | 1 <!doctype html> |
| 2 <html> | |
| 3 <head> | |
| 4 <style> | |
| 5 body { | |
| 6 font-family: Helvetica, Arial, sans-serif; | |
| 7 } | |
| 8 </style> | |
| 9 </head> | |
| 10 <body> | |
| 11 <h1>Simple 16</h1> | |
| 12 <p> | |
| 13 Simple 16 is a toy 16-bit video game console designed with simplicity of implementation in mind. While it is technically a 16-bit system, | |
| 14 it's capabilites are in many ways closer to an 8-bit system. Ultimately, the hope is that Simple 16 is simple enough to provide an easy | |
| 15 introduction for the novice emudev while still containing all the essential features of an older game console. | |
| 16 | |
| 17 </p> | |
| 18 <h2>Table of Contents</h2> | |
| 19 <ul> | |
| 20 <li><a href="#cpu">CPU</a> | |
| 21 <ul> | |
| 22 <li><a href="#cpuover">Overview</a></li> | |
| 23 <li><a href="#cpuregs">Registers</a></li> | |
| 24 <li><a href="#instructions">Instructions</a></li> | |
| 25 <li><a href="#execution">Execution Details</a></li> | |
| 26 <li><a href="#interrupts">Exceptions and Interrupts</a></li> | |
| 27 </ul> | |
| 28 </li> | |
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29 <li><a href="#video">Video</a> |
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30 <ul> |
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31 <li><a href="#vidover">Overview</a></li> |
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32 <li><a href="#vidregs">IO Ports</a></li> |
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33 <li><a href="#vidmem">Memory Map</a></li> |
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34 <li><a href="#vidrender">Rendering</a></li> |
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35 </ul> |
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36 </li> |
| 39 | 37 <li><a href="#audio">Audio</a></li> |
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38 <ul> |
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39 <li><a href="#audover">Overview</a></li> |
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40 <li><a href="#audregs">IO Ports</a></li> |
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41 </ul> |
| 39 | 42 <li><a href="#timer">Timer</a></li> |
| 43 <li><a href="#controllers">Controllers</a></li> | |
| 44 <li><a href="#serial">Serial Port</a></li> | |
| 45 <li><a href="#cart">Cartridge</a></li> | |
| 46 </ul> | |
| 47 <h2 id="cpu">CPU</h2> | |
| 48 <h3 id="cpuover">Overview</h3> | |
| 49 <p> | |
| 50 The Simple 16 CPU is a 16-bit RISC design. It has a main register file of 16 16-bit registers. Additionally, there are five special | |
| 51 purpose registers dedicated to exception processing. It has a flag 16-bit addres space. Instructions are a fixed size and are also 16-bits. | |
| 52 </p> | |
| 53 <h3 id="cpuregs">Registers</h3> | |
| 54 <p> | |
| 55 The first 14 registers in the main file have no fixed function and are named r0 through r13. r14 serves as the program counter and | |
| 56 points to the next instruction to be fetched. More information about instruction fetch and execution can be found in | |
| 57 <a href="#execution">Execution Details</a>. r15 serves as the status register. The status register contains bits corresponding | |
| 58 to the result of the last arithmetic instruction and the interrupt mask. The layout of the status register is given below. | |
| 59 </p> | |
| 60 <table> | |
| 61 <tr> | |
| 62 <th>Bit</th> | |
| 63 <th>Use</th> | |
| 64 <th>Notes</th> | |
| 65 <tr> | |
| 66 <td>15-5</td> | |
| 67 <td>Unused</td> | |
| 68 <td>Should be set to zero.</td> | |
| 69 </tr> | |
| 70 <tr> | |
| 71 <td>4</td> | |
| 72 <td>Negative Flag</td> | |
| 73 <td>Indicates the last result was negative.</td> | |
| 74 </tr> | |
| 75 <tr> | |
| 76 <td>3</td> | |
| 77 <td>Carry Flag</td> | |
| 78 <td>Generally indicates a carry out of bit 15. Last bit shifted out for shift instructions.</td> | |
| 79 </tr> | |
| 80 <tr> | |
| 81 <td>2</td> | |
| 82 <td>Zero fFag</td> | |
| 83 <td>Indicates the last result was zero.</td> | |
| 84 </tr> | |
| 85 <tr> | |
| 86 <td>1</td> | |
| 87 <td>Interrupt 1 enable</td> | |
| 88 <td>Interrupt 1 can be taken when this bit is set.</td> | |
| 89 </tr> | |
| 90 <tr> | |
| 91 <td>0</td> | |
| 92 <td>Interrupt 0 enable</td> | |
| 93 <td>Interrupt 0 can be taken when this bit is set.</td> | |
| 94 </tr> | |
| 95 </table> | |
| 96 <h3 id="instructions">Instructions</h3> | |
| 97 <ul> | |
| 98 <li><a href="#ldim">ldim IM, rD</a></li> | |
| 99 <li><a href="#ldimh">ldimh IM, rD</a></li> | |
| 100 <li><a href="#ld8">ld8 rA, rB, rD</a></li> | |
| 101 <li><a href="#ld16">ld16 rA, rB, rD</a></li> | |
| 102 <li><a href="#str8">str8 rA, rB, rD</a></li> | |
| 103 <li><a href="#str16">str16 rA, rB, rD</a></li> | |
| 104 <li><a href="#add">add rA, rB, rD</a></li> | |
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105 <li><a href="#adc">adc rA, rB, rD</a></li> |
| 39 | 106 <li><a href="#and">and rA, rB, rD</a></li> |
| 107 <li><a href="#or">or rA, rB, rD</a></li> | |
| 108 <li><a href="#xor">xor rA, rB, rD</a></li> | |
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109 <li><a href="#lsl">lsl rA, rB, rD</a></li> |
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110 <li><a href="#lsr">lsr rA, rB, rD</a></li> |
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111 <li><a href="#asr">asr rA, rB, rD</a></li> |
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112 <li><a href="#bcc">bCC LABEL</a></li> |
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113 <li><a href="#mov">mov rA, rD</a></li> |
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114 <li><a href="#neg">neg rA, rD</a></li> |
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115 <li><a href="#not">not rA, rD</a></li> |
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116 <li><a href="#cmp">cmp rA, rD</a></li> |
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117 <li><a href="#call">call rA, rD</a></li> |
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118 <li><a href="#swap">swap rA, rD</a></li> |
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119 <li><a href="#in">in rA, rD</a></li> |
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120 <li><a href="#out">out rA, rD</a></li> |
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121 <li><a href="#ini">ini IM, rD</a></li> |
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122 <li><a href="#outi">outi IM, rD</a></li> |
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123 <li><a href="#addi">addi IM, rD</a></li> |
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124 <li><a href="#andi">andi IM, rD</a></li> |
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125 <li><a href="#ori">ori IM, rD</a></li> |
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126 <li><a href="#lsli">lsli IM, rD</a></li> |
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127 <li><a href="#lsri">lsri IM, rD</a></li> |
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128 <li><a href="#cmpi">cmpi IM, rD</a></li> |
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129 <li><a href="#reti">reti rD</a></li> |
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130 <li><a href="#trap">trap rD</a></li> |
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131 <li><a href="#trapi">trapi IM</a></li> |
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132 <li><a href="#getepc">getepc rD</a></li> |
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133 <li><a href="#setepc">setepc rD</a></li> |
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134 <li><a href="#getesr">getesr rD</a></li> |
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135 <li><a href="#setesr">setser rD</a></li> |
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136 <li><a href="#geteur">geteur rD</a></li> |
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137 <li><a href="#seteur">seteur rD</a></li> |
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138 <li><a href="#getenum">getenum rD</a></li> |
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139 <li><a href="#setenum">setenum rD</a></li> |
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140 <li><a href="#getvbr">getvbr rD</a></li> |
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141 <li><a href="#setvbr">setvbr rD</a></li> |
| 39 | 142 </ul> |
| 143 <h4 id="ldim">ldim IM, rD</h4> | |
| 144 <p> | |
| 145 ldim sign extends an 8-bit immediate value to 16-bits and assigns it to the designated register. | |
| 146 </p> | |
| 147 <p> | |
| 148 <strong>Flags:</strong> No change | |
| 149 </p> | |
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150 <p> |
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151 <strong>Encoding:</strong> |
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152 <table> |
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153 <tr> |
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154 <th>15-12</th> |
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155 <th>11-4</th> |
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156 <th>3-0</th> |
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157 </tr> |
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158 <tr> |
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159 <td>Destination register</td> |
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160 <td>8-bit immediate value</td> |
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161 <td>$0</th> |
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162 </tr> |
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163 </table> |
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164 </p> |
| 39 | 165 <h4 id="ldimh">lidmh IM, rD</h4> |
| 166 <p> | |
| 167 ldimh assigns an 8-bit immediate value to the upper 8-bits of rD. | |
| 168 </p> | |
| 169 <p> | |
| 170 <strong>Flags:</strong> No change | |
| 171 </p> | |
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172 <p> |
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173 <strong>Encoding:</strong> |
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174 <table> |
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175 <tr> |
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176 <th>15-12</th> |
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177 <th>11-4</th> |
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178 <th>3-0</th> |
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179 </tr> |
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180 <tr> |
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181 <td>Destination register</td> |
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182 <td>8-bit immediate value</td> |
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183 <td>$1</th> |
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184 </tr> |
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185 </table> |
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186 </p> |
| 39 | 187 <h4 id="ld8">ld8 rA, rB, rD</h4> |
| 188 <p> | |
| 189 Reads a byte from the address indicated by the sum of rA and rB and loads it into rD | |
| 190 </p> | |
| 191 <p> | |
| 192 <strong>Flags:</strong> No change | |
| 193 </p> | |
|
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194 <p> |
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195 <strong>Encoding:</strong> |
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196 <table> |
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197 <tr> |
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198 <th>15-12</th> |
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199 <th>11-8</th> |
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200 <th>7-4</th> |
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201 <th>3-0</th> |
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202 </tr> |
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203 <tr> |
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204 <td>Destination register</td> |
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205 <td>Source A register</td> |
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206 <td>Source B register</td> |
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207 <td>$2</th> |
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208 </tr> |
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209 </table> |
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210 </p> |
| 39 | 211 <h4 id="ld16">ld16 rA, rB, rD</h4> |
| 212 <p> | |
| 213 Reads a word from the address indicated by the sum of rA and rB and loads it into rD | |
| 214 </p> | |
| 215 <p> | |
| 216 <strong>Flags:</strong> No change | |
| 217 </p> | |
|
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218 <p> |
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219 <strong>Encoding:</strong> |
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220 <table> |
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221 <tr> |
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222 <th>15-12</th> |
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223 <th>11-8</th> |
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224 <th>7-4</th> |
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225 <th>3-0</th> |
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226 </tr> |
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227 <tr> |
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228 <td>Destination register</td> |
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229 <td>Source A register</td> |
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230 <td>Source B register</td> |
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231 <td>$3</th> |
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232 </tr> |
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233 </table> |
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234 </p> |
| 39 | 235 <h4 id="str8">str8 rA, rB, rD</h4> |
| 236 <p> | |
| 237 Writes the byte stored in rD to the address indicated by the sum of rA and rB. | |
| 238 </p> | |
| 239 <p> | |
| 240 <strong>Flags:</strong> No change | |
| 241 </p> | |
|
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242 <p> |
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243 <strong>Encoding:</strong> |
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244 <table> |
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245 <tr> |
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246 <th>15-12</th> |
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247 <th>11-8</th> |
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248 <th>7-4</th> |
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249 <th>3-0</th> |
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250 </tr> |
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251 <tr> |
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252 <td>Register containing value to write (aka rD)</td> |
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253 <td>Source A register</td> |
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254 <td>Source B register</td> |
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255 <td>$4</th> |
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256 </tr> |
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257 </table> |
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258 </p> |
| 39 | 259 <h4 id="str16">str16 rA, rB, rD</h4> |
| 260 <p> | |
| 261 Writes the word stored in rD to the address indicated by the sum of rA and rB. | |
| 262 </p> | |
| 263 <p> | |
| 264 <strong>Flags:</strong> No change | |
| 265 </p> | |
|
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266 <p> |
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267 <strong>Encoding:</strong> |
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268 <table> |
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269 <tr> |
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270 <th>15-12</th> |
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271 <th>11-8</th> |
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272 <th>7-4</th> |
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273 <th>3-0</th> |
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274 </tr> |
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275 <tr> |
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276 <td>Register containing value to write (aka rD)</td> |
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277 <td>Source A register</td> |
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278 <td>Source B register</td> |
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279 <td>$5</th> |
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280 </tr> |
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281 </table> |
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282 </p> |
| 39 | 283 <h4 id="add">add rA, rB, rD</h4> |
| 284 <p> | |
| 285 Adds rA and rB. The result is stored in rD. | |
| 286 </p> | |
| 287 <p> | |
| 288 <strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero | |
| 289 </p> | |
|
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290 <p> |
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291 <strong>Encoding:</strong> |
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292 <table> |
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293 <tr> |
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294 <th>15-12</th> |
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295 <th>11-8</th> |
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296 <th>7-4</th> |
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297 <th>3-0</th> |
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298 </tr> |
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299 <tr> |
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300 <td>Destination register</td> |
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301 <td>Source A register</td> |
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302 <td>Source B register</td> |
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303 <td>$6</th> |
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304 </tr> |
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305 </table> |
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306 </p> |
| 39 | 307 <h4 id="adc">adc rA, rB, rD</h4> |
| 308 <p> | |
| 309 Adds rA, rB and the carry flag. The result is stored in rD. | |
| 310 </p> | |
| 311 <p> | |
|
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312 <strong>Encoding:</strong> |
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313 <table> |
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314 <tr> |
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315 <th>15-12</th> |
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316 <th>11-8</th> |
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317 <th>7-4</th> |
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318 <th>3-0</th> |
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319 </tr> |
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320 <tr> |
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321 <td>Destination register</td> |
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322 <td>Source A register</td> |
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323 <td>Source B register</td> |
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324 <td>$7</th> |
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325 </tr> |
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326 </table> |
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327 </p> |
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328 <p> |
| 39 | 329 <strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero |
| 330 </p> | |
| 331 <h4 id="and">and rA, rB, rD</h4> | |
| 332 <p> | |
| 333 Bitwise and of rA and rB is stored in rD. | |
| 334 </p> | |
| 335 <p> | |
| 336 <strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero | |
| 337 </p> | |
|
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338 <p> |
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339 <strong>Encoding:</strong> |
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340 <table> |
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341 <tr> |
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342 <th>15-12</th> |
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343 <th>11-8</th> |
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344 <th>7-4</th> |
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345 <th>3-0</th> |
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346 </tr> |
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347 <tr> |
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348 <td>Destination register</td> |
|
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349 <td>Source A register</td> |
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350 <td>Source B register</td> |
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351 <td>$8</th> |
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352 </tr> |
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353 </table> |
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354 </p> |
| 39 | 355 <h4 id="or">or rA, rB, rD</h4> |
| 356 <p> | |
| 357 Bitwise or of rA and rB is stored in rD. | |
| 358 </p> | |
| 359 <p> | |
| 360 <strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero | |
| 361 </p> | |
|
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362 <p> |
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363 <strong>Encoding:</strong> |
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364 <table> |
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365 <tr> |
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366 <th>15-12</th> |
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367 <th>11-8</th> |
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368 <th>7-4</th> |
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369 <th>3-0</th> |
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370 </tr> |
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371 <tr> |
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372 <td>Destination register</td> |
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373 <td>Source A register</td> |
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374 <td>Source B register</td> |
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375 <td>$9</th> |
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376 </tr> |
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377 </table> |
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378 </p> |
| 39 | 379 <h4 id="xor">xor rA, rB, rD</h4> |
| 380 <p> | |
| 381 Bitwise exclusive or of rA and rB is stored in rD. | |
| 382 </p> | |
| 383 <p> | |
| 384 <strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero | |
| 385 </p> | |
|
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386 <p> |
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387 <strong>Encoding:</strong> |
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388 <table> |
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389 <tr> |
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390 <th>15-12</th> |
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391 <th>11-8</th> |
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392 <th>7-4</th> |
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393 <th>3-0</th> |
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394 </tr> |
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395 <tr> |
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396 <td>Destination register</td> |
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397 <td>Source A register</td> |
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398 <td>Source B register</td> |
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399 <td>$A</th> |
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400 </tr> |
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401 </table> |
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402 </p> |
| 39 | 403 <h4 id="lsl">lsl rA, rB, rD</h4> |
| 404 <p> | |
| 405 The value in rA is shifted left by rB bits and stored in rD | |
| 406 </p> | |
| 407 <p> | |
| 408 <strong>Flags:</strong> C = last bit shifted out of rA, N = result is negative, Z = result is zero | |
| 409 </p> | |
|
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410 <p> |
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411 <strong>Encoding:</strong> |
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412 <table> |
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413 <tr> |
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414 <th>15-12</th> |
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415 <th>11-8</th> |
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416 <th>7-4</th> |
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417 <th>3-0</th> |
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418 </tr> |
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419 <tr> |
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420 <td>Destination register</td> |
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421 <td>Source A register</td> |
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422 <td>Source B register</td> |
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423 <td>$B</th> |
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424 </tr> |
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425 </table> |
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426 </p> |
| 39 | 427 <h4 id="lsr">lsr rA, rB, rD</h4> |
| 428 <p> | |
| 429 The value in rA is shifted right by rB bits and stored in rD | |
| 430 </p> | |
| 431 <p> | |
| 432 <strong>Flags:</strong> C = last bit shifted out of rA, N = result is negative, Z = result is zero | |
| 433 </p> | |
|
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434 <p> |
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435 <strong>Encoding:</strong> |
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436 <table> |
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437 <tr> |
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438 <th>15-12</th> |
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439 <th>11-8</th> |
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440 <th>7-4</th> |
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441 <th>3-0</th> |
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442 </tr> |
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443 <tr> |
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444 <td>Destination register</td> |
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445 <td>Source A register</td> |
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446 <td>Source B register</td> |
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447 <td>$C</th> |
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448 </tr> |
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449 </table> |
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450 </p> |
| 39 | 451 <h4 id="asr">asr rA, rB, rD</h4> |
| 452 <p> | |
| 453 The value in rA is arithmetically shifted right by rB bits and stored in rD. The most significant bit of rA is copied | |
| 454 into the newly shifted bits. This allows asr to be used for signed division by powers of 2 as the sign is preserved. | |
| 455 </p> | |
|
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456 <p> |
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457 <strong>Flags:</strong> C = last bit shifted out of rA, N = result is negative, Z = result is zero |
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458 </p> |
|
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459 <p> |
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460 <strong>Encoding:</strong> |
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461 <table> |
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462 <tr> |
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463 <th>15-12</th> |
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464 <th>11-8</th> |
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465 <th>7-4</th> |
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466 <th>3-0</th> |
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467 </tr> |
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468 <tr> |
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|
469 <td>Destination register</td> |
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470 <td>Source A register</td> |
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471 <td>Source B register</td> |
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472 <td>$D</th> |
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473 </tr> |
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|
474 </table> |
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|
475 </p> |
|
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|
476 <h4 id="bcc">bCC LABEL</h4> |
| 39 | 477 <p> |
| 478 bCC performs a relative branch if the condition indicated by CC is true. It has a range of 131 instructions forward or | |
| 479 124 instructions backwards. CC must be one of the following values | |
| 480 <table> | |
| 481 <tr> | |
| 482 <th>CC</th> | |
| 483 <th>Mnemonic</th> | |
| 484 <th>Name</th> | |
| 485 <th>Description</th> | |
| 486 </tr> | |
| 487 <tr> | |
| 488 <td>0</td> | |
| 489 <td>ra</td> | |
| 490 <td>bRanch Always</td> | |
| 491 <td>Unconditionall branch</td> | |
| 492 </tr> | |
| 493 <tr> | |
| 494 <td>1</td> | |
| 495 <td>rf</td> | |
| 496 <td>bRanch False</td> | |
| 497 <td>Effectively a nop</td> | |
| 498 </tr> | |
| 499 <tr> | |
| 500 <td>2</td> | |
| 501 <td>eq</td> | |
| 502 <td>EQual</td> | |
| 503 <td>Branch if zero flag is 1</td> | |
| 504 </tr> | |
| 505 <tr> | |
| 506 <td>3</td> | |
| 507 <td>ne</td> | |
| 508 <td>Not Equal</td> | |
| 509 <td>Branch if zero flag is 0</td> | |
| 510 </tr> | |
| 511 <tr> | |
| 512 <td>4</td> | |
| 513 <td>mi</td> | |
| 514 <td>MInus</td> | |
| 515 <td>Branch if negative flag is 1</td> | |
| 516 </tr> | |
| 517 <tr> | |
| 518 <td>5</td> | |
| 519 <td>pl</td> | |
| 520 <td>PLus</td> | |
| 521 <td>Branch if negative flag is 0</td> | |
| 522 </tr> | |
| 523 <tr> | |
| 524 <td>6</td> | |
| 525 <td>cs</td> | |
| 526 <td>Carry Set</td> | |
| 527 <td>Branch if carry flag is 1. Unsigned "less than" when used with cmp</td> | |
| 528 </tr> | |
| 529 <tr> | |
| 530 <td>7</td> | |
| 531 <td>cc</td> | |
| 532 <td>Carry Clear</td> | |
| 533 <td>Branch if carry flag is 1. Unsigned "greater or equal" when used with cmp</td> | |
| 534 </tr> | |
| 535 <tr> | |
| 536 <td>8</td> | |
| 537 <td>gr</td> | |
| 538 <td>Greater</td> | |
| 539 <td>Branch if carry flag is 0 and the zero flag is zero. Unsigned "greater" when used with cmp</td> | |
| 540 </tr> | |
| 541 <tr> | |
| 542 <td>9</td> | |
| 543 <td>le</td> | |
| 544 <td>Less or Equal</td> | |
| 545 <td>Branch if carry flag is 1 or the zero flag is 1. Unsigned "lesser or equal" when used with cmp</td> | |
| 546 </tr> | |
| 547 </table> | |
| 548 Use of CC values greater than 9 will result in an invalid instruction exception. | |
| 549 </p> | |
|
40
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|
550 <p> |
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|
551 <strong>Flags:</strong> No change |
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|
552 </p> |
|
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|
553 |
|
a64e11e48a41
Added encoding for a bunch of instructions
Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
554 <p> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
555 <strong>Encoding:</strong> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
556 <table> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
557 <tr> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
558 <th>15-12</th> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
559 <th>11-4</th> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
560 <th>3-0</th> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
561 </tr> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
562 <tr> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
563 <td>CC</td> |
|
a64e11e48a41
Added encoding for a bunch of instructions
Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
564 <td>Signed 8-bit offset. Offset is multiplied by two before being added to PC</td> |
|
a64e11e48a41
Added encoding for a bunch of instructions
Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
565 <td>$E</th> |
|
a64e11e48a41
Added encoding for a bunch of instructions
Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
566 </tr> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
567 </table> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
568 </p> |
| 39 | 569 <h4 id="mov">mov rA, rD</h4> |
| 570 <p> | |
| 571 Stores the value of rA in rD. This can be used as a return or jump instruction if rD is PC. | |
| 572 </p> | |
|
40
413e7b9c0db1
Added flag change documentation for all instructions. Added hyperlinks to individual instructions. Added overviews for all the peripherals
Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
573 <p> |
|
413e7b9c0db1
Added flag change documentation for all instructions. Added hyperlinks to individual instructions. Added overviews for all the peripherals
Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
574 <strong>Flags:</strong> No change |
|
413e7b9c0db1
Added flag change documentation for all instructions. Added hyperlinks to individual instructions. Added overviews for all the peripherals
Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
575 </p> |
|
42
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
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|
576 <p> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
577 <strong>Encoding:</strong> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
578 <table> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
579 <tr> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
580 <th>15-12</th> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
581 <th>11-8</th> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
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|
582 <th>7-4</th> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
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|
583 <th>3-0</th> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
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diff
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|
584 </tr> |
|
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Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
585 <tr> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
586 <td>Destination register</td> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
587 <td>Source A register</td> |
|
a64e11e48a41
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40
diff
changeset
|
588 <td>$0</td> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
589 <td>$F</th> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
590 </tr> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
591 </table> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
592 </p> |
| 39 | 593 <h4 id="neg">neg rA, rD</h4> |
| 594 <p> | |
| 595 Calculates the 2s complement of rA and stores it in rD. This can be used in combination with add to implement subtraction. | |
| 596 </p> | |
|
40
413e7b9c0db1
Added flag change documentation for all instructions. Added hyperlinks to individual instructions. Added overviews for all the peripherals
Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
597 <p> |
|
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
598 <strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero |
|
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
599 </p> |
|
42
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
600 <p> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
601 <strong>Encoding:</strong> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
602 <table> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
603 <tr> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
604 <th>15-12</th> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
605 <th>11-8</th> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
606 <th>7-4</th> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
607 <th>3-0</th> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
608 </tr> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
609 <tr> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
610 <td>Destination register</td> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
611 <td>Source A register</td> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
612 <td>$1</td> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
613 <td>$F</th> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
614 </tr> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
615 </table> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
616 </p> |
| 39 | 617 <h4 id="not">not rA, rD</h4> |
| 618 <p> | |
| 619 Calculates the 1s complement of rA and stores it in rD. | |
| 620 </p> | |
|
40
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
621 <p> |
|
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
622 <strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero |
|
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
623 </p> |
|
42
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
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diff
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|
624 <p> |
|
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Michael Pavone <pavone@retrodev.com>
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|
625 <strong>Encoding:</strong> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
626 <table> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
627 <tr> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
628 <th>15-12</th> |
|
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diff
changeset
|
629 <th>11-8</th> |
|
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parents:
40
diff
changeset
|
630 <th>7-4</th> |
|
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40
diff
changeset
|
631 <th>3-0</th> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
632 </tr> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
633 <tr> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
634 <td>Destination register</td> |
|
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
635 <td>Source A register</td> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
636 <td>$2</td> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
637 <td>$F</th> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
638 </tr> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
639 </table> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
640 </p> |
| 39 | 641 <h4 id="cmp">cmp rA, rD</h4> |
| 642 <p> | |
| 643 Subtracts rA from rD and discards the result, but still updates flags. | |
| 644 </p> | |
|
40
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
645 <p> |
|
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
646 <strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero |
|
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
647 </p> |
|
42
a64e11e48a41
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diff
changeset
|
648 <p> |
|
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40
diff
changeset
|
649 <strong>Encoding:</strong> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
650 <table> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
651 <tr> |
|
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
652 <th>15-12</th> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
653 <th>11-8</th> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
654 <th>7-4</th> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
655 <th>3-0</th> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
656 </tr> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
657 <tr> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
658 <td>Destination register</td> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
659 <td>Source A register</td> |
|
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parents:
40
diff
changeset
|
660 <td>$3</td> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
661 <td>$F</th> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
662 </tr> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
663 </table> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
664 </p> |
| 39 | 665 <h4 id="call">call rA, rD</h4> |
| 666 <p> | |
| 667 Stores the address of the next instruction in rD and sets PC to the value in rA. Used for calling subroutines. | |
| 668 </p> | |
|
40
413e7b9c0db1
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parents:
39
diff
changeset
|
669 <p> |
|
413e7b9c0db1
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parents:
39
diff
changeset
|
670 <strong>Flags:</strong> No change |
|
413e7b9c0db1
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39
diff
changeset
|
671 </p> |
|
42
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parents:
40
diff
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|
672 <p> |
|
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40
diff
changeset
|
673 <strong>Encoding:</strong> |
|
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parents:
40
diff
changeset
|
674 <table> |
|
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40
diff
changeset
|
675 <tr> |
|
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parents:
40
diff
changeset
|
676 <th>15-12</th> |
|
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40
diff
changeset
|
677 <th>11-8</th> |
|
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parents:
40
diff
changeset
|
678 <th>7-4</th> |
|
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40
diff
changeset
|
679 <th>3-0</th> |
|
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parents:
40
diff
changeset
|
680 </tr> |
|
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40
diff
changeset
|
681 <tr> |
|
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40
diff
changeset
|
682 <td>Destination register</td> |
|
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40
diff
changeset
|
683 <td>Source A register</td> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
684 <td>$4</td> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
685 <td>$F</th> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
686 </tr> |
|
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
687 </table> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
688 </p> |
| 39 | 689 <h4 id="swap">swap rA, rD</h4> |
| 690 <p> | |
| 691 Swaps the values in rA and rD. | |
| 692 </p> | |
|
40
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
693 <p> |
|
413e7b9c0db1
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parents:
39
diff
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|
694 <strong>Flags:</strong> No change |
|
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
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|
695 </p> |
|
42
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diff
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|
696 <p> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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40
diff
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|
697 <strong>Encoding:</strong> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
698 <table> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
699 <tr> |
|
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Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
700 <th>15-12</th> |
|
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
701 <th>11-8</th> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
702 <th>7-4</th> |
|
a64e11e48a41
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40
diff
changeset
|
703 <th>3-0</th> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
704 </tr> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
705 <tr> |
|
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
706 <td>Destination register</td> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
707 <td>Source A register</td> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
708 <td>$5</td> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
709 <td>$F</th> |
|
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
710 </tr> |
|
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Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
711 </table> |
|
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
712 </p> |
| 39 | 713 <h4 id="in">in rA, rD</h4> |
| 714 <p> | |
| 715 Reads a word from the IO port indicated by rA and stores it in rD. | |
| 716 </p> | |
|
40
413e7b9c0db1
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39
diff
changeset
|
717 <p> |
|
413e7b9c0db1
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39
diff
changeset
|
718 <strong>Flags:</strong> No change |
|
413e7b9c0db1
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39
diff
changeset
|
719 </p> |
| 39 | 720 <h4 id="out">out rA, rD</h4> |
| 721 <p> | |
| 722 Writes the word stored in rD to the IO port indicated by rA. | |
| 723 </p> | |
|
40
413e7b9c0db1
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39
diff
changeset
|
724 <p> |
|
413e7b9c0db1
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diff
changeset
|
725 <strong>Flags:</strong> No change |
|
413e7b9c0db1
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39
diff
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|
726 </p> |
| 39 | 727 <h4 id="ini">ini IM, rD</h4> |
| 728 <p> | |
| 729 Reads a word from the IO port indicated by IM and stores it in rD. IM can range from 0 to 15. | |
| 730 </p> | |
|
40
413e7b9c0db1
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diff
changeset
|
731 <p> |
|
413e7b9c0db1
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diff
changeset
|
732 <strong>Flags:</strong> No change |
|
413e7b9c0db1
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39
diff
changeset
|
733 </p> |
| 39 | 734 <h4 id="outi">outi</h4> |
| 735 <p> | |
| 736 Writes the word stored in rD to the IO port indicated by IM. IM can range from 0 to 15. | |
| 737 </p> | |
|
40
413e7b9c0db1
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39
diff
changeset
|
738 <p> |
|
413e7b9c0db1
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39
diff
changeset
|
739 <strong>Flags:</strong> No change |
|
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diff
changeset
|
740 </p> |
| 39 | 741 <h4 id="addi">addi IM, rD</h4> |
| 742 <p> | |
| 743 Adds IM to the value in rD and stores the result in rD. IM range from -8 to -1 or 1 to 8. A value of 0 is used to indicate 8. | |
| 744 </p> | |
|
40
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
745 <p> |
|
413e7b9c0db1
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39
diff
changeset
|
746 <strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero |
|
413e7b9c0db1
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diff
changeset
|
747 </p> |
| 39 | 748 <h4 id="andi">andi IM, rD</h4> |
| 749 <p> | |
| 750 Performs a logical and of IM and the value in rD and stores the result in rD. IM can range from -8 to -1 or 1 to 8. A value of 0 is used to indicate 8. | |
| 751 </p> | |
|
40
413e7b9c0db1
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diff
changeset
|
752 <p> |
|
413e7b9c0db1
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39
diff
changeset
|
753 <strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero |
|
413e7b9c0db1
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39
diff
changeset
|
754 </p> |
| 39 | 755 <h4 id="ori">ori IM, rD</h4> |
| 756 <p> | |
| 757 Performs a logical or of IM and the value in rD and stores the result in rD. IM can range from-8 to -1 or 1 to 8. A value of 0 is used to indicate 8. | |
| 758 </p> | |
|
40
413e7b9c0db1
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39
diff
changeset
|
759 <p> |
|
413e7b9c0db1
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39
diff
changeset
|
760 <strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero |
|
413e7b9c0db1
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39
diff
changeset
|
761 </p> |
| 39 | 762 <h4 id="lsli">lsli IM, rD</h4> |
| 763 <p> | |
| 764 Shifts the value in rD IM bits to the left. IM can range from 1 to 8. | |
| 765 </p> | |
|
40
413e7b9c0db1
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39
diff
changeset
|
766 <p> |
|
413e7b9c0db1
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39
diff
changeset
|
767 <strong>Flags:</strong> C = last bit shifted out of rA, N = result is negative, Z = result is zero |
|
413e7b9c0db1
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39
diff
changeset
|
768 </p> |
| 39 | 769 <h4 id="lsri">lsri IM, rD</h4> |
| 770 <p> | |
| 771 Shifts the value in rD IM bits to the right. IM can range from 1 to 8. | |
| 772 </p> | |
|
40
413e7b9c0db1
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39
diff
changeset
|
773 <p> |
|
413e7b9c0db1
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39
diff
changeset
|
774 <strong>Flags:</strong> C = last bit shifted out of rA, N = result is negative, Z = result is zero |
|
413e7b9c0db1
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diff
changeset
|
775 </p> |
| 39 | 776 <h4 id="cmpi">cmpi IM, rd</h4> |
| 777 <p> | |
| 778 Subtracts IM from rD and discards the result, but updates flags. IM can range from -8 to 7. | |
| 779 </p> | |
|
40
413e7b9c0db1
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39
diff
changeset
|
780 <p> |
|
413e7b9c0db1
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diff
changeset
|
781 <strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero |
|
413e7b9c0db1
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39
diff
changeset
|
782 </p> |
| 39 | 783 <h4 id="reti">reti rD</h4> |
| 784 <p> | |
| 785 Sets rD to the value storeed in EUR, SR to the value stored in ESR and PC to the value stored in EPC. This instruction is used for returning from an | |
| 786 exception or interrupt. | |
| 787 </p> | |
|
40
413e7b9c0db1
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39
diff
changeset
|
788 <p> |
|
413e7b9c0db1
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diff
changeset
|
789 <strong>Flags:</strong> Updated corresponding to the value in ESR. |
|
413e7b9c0db1
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39
diff
changeset
|
790 </p> |
| 39 | 791 <h4 id="trap">trap rD</h4> |
| 792 <p> | |
| 793 Causes an exception to be taken to the vector indicated by rD. | |
| 794 </p> | |
|
40
413e7b9c0db1
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39
diff
changeset
|
795 <p> |
|
413e7b9c0db1
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39
diff
changeset
|
796 <strong>Flags:</strong> Condition code flags unchanged, interrupt enable bits cleared. |
|
413e7b9c0db1
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39
diff
changeset
|
797 </p> |
| 39 | 798 <h4 id="trapi">trapi IM</h4> |
| 799 <p> | |
|
40
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diff
changeset
|
800 Causes an exception to be taken to the vector indicated by IM |
|
413e7b9c0db1
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diff
changeset
|
801 </p> |
|
413e7b9c0db1
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diff
changeset
|
802 <p> |
|
413e7b9c0db1
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39
diff
changeset
|
803 <strong>Flags:</strong> Condition code flags unchanged, interrupt enable bits cleared. |
| 39 | 804 </p> |
| 805 <h4 id="getepc">getepc rD</h4> | |
| 806 <p> | |
| 807 Stores the value of EPC in rD. | |
| 808 </p> | |
|
40
413e7b9c0db1
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39
diff
changeset
|
809 <p> |
|
413e7b9c0db1
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diff
changeset
|
810 <strong>Flags:</strong> No change |
|
413e7b9c0db1
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39
diff
changeset
|
811 </p> |
|
413e7b9c0db1
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39
diff
changeset
|
812 <h4 id="setepc">setepc rD</h4> |
| 39 | 813 <p> |
| 814 Stores the vaule of rD in EPC. | |
| 815 </p> | |
| 816 <p> | |
|
40
413e7b9c0db1
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diff
changeset
|
817 <strong>Flags:</strong> No change |
|
413e7b9c0db1
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diff
changeset
|
818 </p> |
|
413e7b9c0db1
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diff
changeset
|
819 <h4 id="getesr">getesr rD</h4> |
|
413e7b9c0db1
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changeset
|
820 <p> |
|
413e7b9c0db1
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diff
changeset
|
821 Stores the value of ESR in rD. |
| 39 | 822 </p> |
| 823 <p> | |
|
40
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diff
changeset
|
824 <strong>Flags:</strong> No change |
|
413e7b9c0db1
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changeset
|
825 </p> |
|
413e7b9c0db1
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diff
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|
826 <h4 id="setesr">setesr rD</h4> |
|
413e7b9c0db1
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|
827 <p> |
|
413e7b9c0db1
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diff
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|
828 Stores the value of rD in ESR. |
| 39 | 829 </p> |
| 830 <p> | |
|
40
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diff
changeset
|
831 <strong>Flags:</strong> No change |
|
413e7b9c0db1
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diff
changeset
|
832 </p> |
|
413e7b9c0db1
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|
833 <h4 id="geteur">geteur rD</h4> |
|
413e7b9c0db1
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changeset
|
834 <p> |
|
413e7b9c0db1
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diff
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|
835 Stores the value of EUR in rD. |
| 39 | 836 </p> |
| 837 <p> | |
|
40
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39
diff
changeset
|
838 <strong>Flags:</strong> No change |
|
413e7b9c0db1
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diff
changeset
|
839 </p> |
|
413e7b9c0db1
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39
diff
changeset
|
840 <h4 id="seteur">seteur rD</h4> |
|
413e7b9c0db1
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39
diff
changeset
|
841 <p> |
|
413e7b9c0db1
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39
diff
changeset
|
842 Stores the value of rd in EUR. |
| 39 | 843 </p> |
| 844 <p> | |
|
40
413e7b9c0db1
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39
diff
changeset
|
845 <strong>Flags:</strong> No change |
|
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846 </p> |
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847 <h4 id="getenum">getenum rD</h4> |
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848 <p> |
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849 Stores the value of ENUM in rD. |
| 39 | 850 </p> |
| 851 <p> | |
|
40
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852 <strong>Flags:</strong> No change |
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853 </p> |
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854 <h4 id="setenum">setenum rD</h4> |
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855 <p> |
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856 Stores the value of rd in ENUM. |
| 39 | 857 </p> |
| 858 <p> | |
|
40
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859 <strong>Flags:</strong> No change |
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413e7b9c0db1
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860 </p> |
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861 <h4 id="getvbr">getvbr rD</h4> |
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862 <p> |
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863 Stores the value of VBR in rD. |
| 39 | 864 </p> |
|
40
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865 <p> |
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866 <strong>Flags:</strong> No change |
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867 </p> |
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868 <h4 id="setvbr">setvbr rD</h4> |
| 39 | 869 <p> |
|
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870 Stores the valueof rD in VBR. |
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871 </p> |
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872 <p> |
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873 <strong>Flags:</strong> No change |
| 39 | 874 </p> |
| 875 <h2 id="video">Video</h2> | |
|
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876 <h3 id="vidover">Overview</h3> |
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877 <p> |
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878 Simple 16 features a tile-based video processor using 8x8 pixel tiles. It supports a single background plane with a fixed width of 64 tiles and configurable height. |
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879 64 sprites can be displayed simultaneously and 20 can be displayed on each line. Each sprite can either be 8x8 or 16x16 pixels and can use either of the first two |
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880 16 color palettes. The background plane can make use of all 4 palettes. |
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881 </p> |
| 39 | 882 <h2 id="audio">Audio</h2> |
|
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883 <h3 id="audover">Overview</h3> |
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884 <p> |
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885 Simple 16 has four square-wave tone generators with a 16-bit period and an 8-bit volume. The special value of 0 for the period causes the volume to be output constantly |
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886 allowing the volume register to be used as a simple 8-bit DAC. |
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887 </p> |
| 39 | 888 <h2 id="timer">Timer</h2> |
|
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889 <h3 id="timeover">Overview</h3> |
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890 <p> |
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891 Simple 16 has a single timer with a 16-bit period. Interrupt 0 is triggered on timer expiration. |
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892 </p> |
| 39 | 893 <h2 id="controllers">Controllers</h2> |
|
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894 <h3 id="contover">Overview</h3> |
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895 <p> |
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896 Simple 16 supports 2 controllers, each with a D-pad and 8 buttons configured in either an SNES (4 action buttons on the face + 2 shoulder buttons + Start and Select) |
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897 or Genesis 6-button controller (6 action buttons on the face + Start and Mode) arrangement. In this document, the buttons are given using the Genesis naming scheme. |
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898 For a controller following the SNES layout, the right trigger is 'C', the left trigger is 'Z' and 'Select' is 'Mode'. |
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899 </p> |
| 39 | 900 <h2 id="serial">Serial Port</h2> |
|
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|
901 <h3>Overview</h3> |
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902 <p> |
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|
903 This port can be thought of a simple UART for debugging purposes. In an emulator, a write should result in a byte being written to stdout and a read should return |
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|
904 a byte read from stdin. This peripheral can be omitted in which case writes should be ignored and reads should return $FFFF. The primary purpose of this port is |
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|
905 to enable easy debugging of the CPU core before other, more complicated, peripherals are working. |
| 39 | 906 <h2 id="cart">Cartridge</h2> |
|
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907 <h3>Overview</h3> |
|
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|
908 <p> |
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|
909 Simple 16 allows for 48KB of flat mapped cartridge ROM. Future revisions may allow banking. |
|
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|
910 </p> |
| 39 | 911 </body> |
| 912 </html> |