Mercurial > repos > simple16
annotate simple16.html @ 56:fa9cf7108ab7
Add 8bpp picture example
author | Michael Pavone <pavone@retrodev.com> |
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date | Wed, 31 Aug 2016 23:50:20 -0700 |
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39 | 1 <!doctype html> |
2 <html> | |
3 <head> | |
4 <style> | |
5 body { | |
6 font-family: Helvetica, Arial, sans-serif; | |
7 } | |
8 </style> | |
9 </head> | |
10 <body> | |
11 <h1>Simple 16</h1> | |
12 <p> | |
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13 Simple 16 is a toy 16-bit video game console designed with simplicity of implementation in mind. The hope is that |
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14 Simple 16 is simple enough to provide an easy introduction for the novice emudev while still containing all the |
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15 essential features of an older game console and providing sufficient capabilities to support compelling games. |
39 | 16 |
17 </p> | |
18 <h2>Table of Contents</h2> | |
19 <ul> | |
20 <li><a href="#cpu">CPU</a> | |
21 <ul> | |
22 <li><a href="#cpuover">Overview</a></li> | |
23 <li><a href="#cpuregs">Registers</a></li> | |
24 <li><a href="#instructions">Instructions</a></li> | |
25 <li><a href="#execution">Execution Details</a></li> | |
26 <li><a href="#interrupts">Exceptions and Interrupts</a></li> | |
27 </ul> | |
28 </li> | |
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29 <li><a href="#video">Video</a> |
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30 <ul> |
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31 <li><a href="#vidover">Overview</a></li> |
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32 <li><a href="#vidregs">IO Ports</a></li> |
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33 <li><a href="#vidmem">Memory Map</a></li> |
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34 <li><a href="#vidrender">Rendering</a></li> |
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35 </ul> |
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36 </li> |
39 | 37 <li><a href="#audio">Audio</a></li> |
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38 <ul> |
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39 <li><a href="#audover">Overview</a></li> |
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40 <li><a href="#audregs">IO Ports</a></li> |
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41 </ul> |
39 | 42 <li><a href="#timer">Timer</a></li> |
43 <li><a href="#controllers">Controllers</a></li> | |
44 <li><a href="#serial">Serial Port</a></li> | |
45 <li><a href="#cart">Cartridge</a></li> | |
46 </ul> | |
47 <h2 id="cpu">CPU</h2> | |
48 <h3 id="cpuover">Overview</h3> | |
49 <p> | |
50 The Simple 16 CPU is a 16-bit RISC design. It has a main register file of 16 16-bit registers. Additionally, there are five special | |
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51 purpose registers dedicated to exception processing and an additional special register for holding the upper bits of the program counter. |
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52 It has a 23-bit addres space addressable with 16-bit offsets. Instructions are a fixed size and are also 16-bits. |
39 | 53 </p> |
54 <h3 id="cpuregs">Registers</h3> | |
55 <p> | |
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56 The first 12 registers in the main file have no fixed function and are named r0 through r11. r12 holds the upper 8-bits of the |
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57 upper and lower data segments and is also named db. r13 holds the stack pointer and is also named sp. r14 serves as the program |
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58 counter and points to the next instruction to be fetched. More information about instruction fetch and execution can be found in |
39 | 59 <a href="#execution">Execution Details</a>. r15 serves as the status register. The status register contains bits corresponding |
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60 to the result of the last arithmetic instruction and the interrupt mask. It also contains the uppper 7-bits of the stack segment. |
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61 The layout of the status register is given below. |
39 | 62 </p> |
63 <table> | |
64 <tr> | |
65 <th>Bit</th> | |
66 <th>Use</th> | |
67 <th>Notes</th> | |
68 <tr> | |
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69 <td>15</td> |
39 | 70 <td>Unused</td> |
71 <td>Should be set to zero.</td> | |
72 </tr> | |
73 <tr> | |
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74 <td>14-8</td> |
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75 <td>Stack Segment</td> |
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76 <td>Bits 8-14 of the 23-bit address for stack-relative load and stores</td> |
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77 </tr> |
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78 <tr> |
39 | 79 <td>4</td> |
80 <td>Negative Flag</td> | |
81 <td>Indicates the last result was negative.</td> | |
82 </tr> | |
83 <tr> | |
84 <td>3</td> | |
85 <td>Carry Flag</td> | |
86 <td>Generally indicates a carry out of bit 15. Last bit shifted out for shift instructions.</td> | |
87 </tr> | |
88 <tr> | |
89 <td>2</td> | |
90 <td>Zero fFag</td> | |
91 <td>Indicates the last result was zero.</td> | |
92 </tr> | |
93 <tr> | |
94 <td>1</td> | |
95 <td>Interrupt 1 enable</td> | |
96 <td>Interrupt 1 can be taken when this bit is set.</td> | |
97 </tr> | |
98 <tr> | |
99 <td>0</td> | |
100 <td>Interrupt 0 enable</td> | |
101 <td>Interrupt 0 can be taken when this bit is set.</td> | |
102 </tr> | |
103 </table> | |
104 <h3 id="instructions">Instructions</h3> | |
105 <ul> | |
106 <li><a href="#ldim">ldim IM, rD</a></li> | |
107 <li><a href="#ldimh">ldimh IM, rD</a></li> | |
108 <li><a href="#ld8">ld8 rA, rB, rD</a></li> | |
109 <li><a href="#ld16">ld16 rA, rB, rD</a></li> | |
110 <li><a href="#str8">str8 rA, rB, rD</a></li> | |
111 <li><a href="#str16">str16 rA, rB, rD</a></li> | |
112 <li><a href="#add">add rA, rB, rD</a></li> | |
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113 <li><a href="#adc">adc rA, rB, rD</a></li> |
39 | 114 <li><a href="#and">and rA, rB, rD</a></li> |
115 <li><a href="#or">or rA, rB, rD</a></li> | |
116 <li><a href="#xor">xor rA, rB, rD</a></li> | |
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117 <li><a href="#lsl">lsl rA, rB, rD</a></li> |
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118 <li><a href="#lsr">lsr rA, rB, rD</a></li> |
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119 <li><a href="#asr">asr rA, rB, rD</a></li> |
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120 <li><a href="#bcc">bCC LABEL</a></li> |
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121 <li><a href="#mov">mov rA, rD</a></li> |
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122 <li><a href="#neg">neg rA, rD</a></li> |
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123 <li><a href="#not">not rA, rD</a></li> |
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124 <li><a href="#cmp">cmp rA, rD</a></li> |
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125 <li><a href="#call">call rA, rD</a></li> |
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126 <li><a href="#swap">swap rA, rD</a></li> |
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127 <li><a href="#longjmp">longjmp</a></li> |
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128 <li><a href="#ini">ini IM, rD</a></li> |
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129 <li><a href="#outi">outi IM, rD</a></li> |
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130 <li><a href="#addi">addi IM, rD</a></li> |
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131 <li><a href="#andi">andi IM, rD</a></li> |
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132 <li><a href="#ori">ori IM, rD</a></li> |
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133 <li><a href="#xori">xori IM, rD</a></li> |
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134 <li><a href="#lsli">lsli IM, rD</a></li> |
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135 <li><a href="#lsri">lsri IM, rD</a></li> |
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136 <li><a href="#cmpi">cmpi IM, rD</a></li> |
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137 <li><a href="#reti">reti rD</a></li> |
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138 <li><a href="#trapi">trapi IM</a></li> |
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139 <li><a href="#push">push rD</a></li> |
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140 <li><a href="#pop">pop rD</a></li> |
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141 <li><a href="#getepc">getpch rD</a></li> |
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142 <li><a href="#setepc">setpch rD</a></li> |
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143 <li><a href="#getepc">getepc rD</a></li> |
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144 <li><a href="#setepc">setepc rD</a></li> |
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145 <li><a href="#getesr">getesr rD</a></li> |
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146 <li><a href="#setesr">setser rD</a></li> |
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147 <li><a href="#geteur">geteur rD</a></li> |
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148 <li><a href="#seteur">seteur rD</a></li> |
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149 <li><a href="#getenum">getenum rD</a></li> |
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150 <li><a href="#setenum">setenum rD</a></li> |
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151 <li><a href="#getvbr">getvbr rD</a></li> |
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152 <li><a href="#setvbr">setvbr rD</a></li> |
39 | 153 </ul> |
154 <h4 id="ldim">ldim IM, rD</h4> | |
155 <p> | |
156 ldim sign extends an 8-bit immediate value to 16-bits and assigns it to the designated register. | |
157 </p> | |
158 <p> | |
159 <strong>Flags:</strong> No change | |
160 </p> | |
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161 <p> |
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162 <strong>Encoding:</strong> |
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163 <table> |
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164 <tr> |
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165 <th>15-12</th> |
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166 <th>11-4</th> |
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167 <th>3-0</th> |
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168 </tr> |
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169 <tr> |
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170 <td>Destination register</td> |
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171 <td>8-bit immediate value</td> |
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172 <td>$0</th> |
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173 </tr> |
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174 </table> |
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175 </p> |
39 | 176 <h4 id="ldimh">lidmh IM, rD</h4> |
177 <p> | |
178 ldimh assigns an 8-bit immediate value to the upper 8-bits of rD. | |
179 </p> | |
180 <p> | |
181 <strong>Flags:</strong> No change | |
182 </p> | |
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183 <p> |
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184 <strong>Encoding:</strong> |
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185 <table> |
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186 <tr> |
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187 <th>15-12</th> |
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188 <th>11-4</th> |
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189 <th>3-0</th> |
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190 </tr> |
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191 <tr> |
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192 <td>Destination register</td> |
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193 <td>8-bit immediate value</td> |
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194 <td>$1</th> |
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195 </tr> |
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196 </table> |
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197 </p> |
39 | 198 <h4 id="ld8">ld8 rA, rB, rD</h4> |
199 <p> | |
200 Reads a byte from the address indicated by the sum of rA and rB and loads it into rD | |
201 </p> | |
202 <p> | |
203 <strong>Flags:</strong> No change | |
204 </p> | |
42
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205 <p> |
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206 <strong>Encoding:</strong> |
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207 <table> |
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208 <tr> |
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209 <th>15-12</th> |
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210 <th>11-8</th> |
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211 <th>7-4</th> |
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212 <th>3-0</th> |
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213 </tr> |
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214 <tr> |
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215 <td>Destination register</td> |
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216 <td>Source A register</td> |
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217 <td>Source B register</td> |
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218 <td>$2</th> |
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219 </tr> |
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220 </table> |
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221 </p> |
39 | 222 <h4 id="ld16">ld16 rA, rB, rD</h4> |
223 <p> | |
224 Reads a word from the address indicated by the sum of rA and rB and loads it into rD | |
225 </p> | |
226 <p> | |
227 <strong>Flags:</strong> No change | |
228 </p> | |
42
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229 <p> |
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230 <strong>Encoding:</strong> |
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231 <table> |
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232 <tr> |
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233 <th>15-12</th> |
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234 <th>11-8</th> |
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235 <th>7-4</th> |
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236 <th>3-0</th> |
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237 </tr> |
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238 <tr> |
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239 <td>Destination register</td> |
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240 <td>Source A register</td> |
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241 <td>Source B register</td> |
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242 <td>$3</th> |
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243 </tr> |
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244 </table> |
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245 </p> |
39 | 246 <h4 id="str8">str8 rA, rB, rD</h4> |
247 <p> | |
248 Writes the byte stored in rD to the address indicated by the sum of rA and rB. | |
249 </p> | |
250 <p> | |
251 <strong>Flags:</strong> No change | |
252 </p> | |
42
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253 <p> |
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254 <strong>Encoding:</strong> |
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255 <table> |
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256 <tr> |
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257 <th>15-12</th> |
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258 <th>11-8</th> |
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259 <th>7-4</th> |
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260 <th>3-0</th> |
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261 </tr> |
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262 <tr> |
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263 <td>Register containing value to write (aka rD)</td> |
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264 <td>Source A register</td> |
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265 <td>Source B register</td> |
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266 <td>$4</th> |
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267 </tr> |
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268 </table> |
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269 </p> |
39 | 270 <h4 id="str16">str16 rA, rB, rD</h4> |
271 <p> | |
272 Writes the word stored in rD to the address indicated by the sum of rA and rB. | |
273 </p> | |
274 <p> | |
275 <strong>Flags:</strong> No change | |
276 </p> | |
42
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277 <p> |
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278 <strong>Encoding:</strong> |
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279 <table> |
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280 <tr> |
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281 <th>15-12</th> |
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282 <th>11-8</th> |
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283 <th>7-4</th> |
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284 <th>3-0</th> |
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285 </tr> |
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286 <tr> |
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287 <td>Register containing value to write (aka rD)</td> |
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288 <td>Source A register</td> |
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289 <td>Source B register</td> |
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290 <td>$5</th> |
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291 </tr> |
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292 </table> |
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293 </p> |
39 | 294 <h4 id="add">add rA, rB, rD</h4> |
295 <p> | |
296 Adds rA and rB. The result is stored in rD. | |
297 </p> | |
298 <p> | |
299 <strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero | |
300 </p> | |
42
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301 <p> |
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302 <strong>Encoding:</strong> |
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303 <table> |
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304 <tr> |
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305 <th>15-12</th> |
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306 <th>11-8</th> |
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307 <th>7-4</th> |
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308 <th>3-0</th> |
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309 </tr> |
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310 <tr> |
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311 <td>Destination register</td> |
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312 <td>Source A register</td> |
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313 <td>Source B register</td> |
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314 <td>$6</th> |
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315 </tr> |
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316 </table> |
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317 </p> |
39 | 318 <h4 id="adc">adc rA, rB, rD</h4> |
319 <p> | |
320 Adds rA, rB and the carry flag. The result is stored in rD. | |
321 </p> | |
322 <p> | |
42
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323 <strong>Encoding:</strong> |
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324 <table> |
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325 <tr> |
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326 <th>15-12</th> |
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327 <th>11-8</th> |
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328 <th>7-4</th> |
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329 <th>3-0</th> |
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330 </tr> |
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331 <tr> |
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332 <td>Destination register</td> |
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333 <td>Source A register</td> |
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334 <td>Source B register</td> |
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335 <td>$7</th> |
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336 </tr> |
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337 </table> |
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338 </p> |
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339 <p> |
39 | 340 <strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero |
341 </p> | |
342 <h4 id="and">and rA, rB, rD</h4> | |
343 <p> | |
344 Bitwise and of rA and rB is stored in rD. | |
345 </p> | |
346 <p> | |
347 <strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero | |
348 </p> | |
42
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349 <p> |
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350 <strong>Encoding:</strong> |
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351 <table> |
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352 <tr> |
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353 <th>15-12</th> |
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354 <th>11-8</th> |
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355 <th>7-4</th> |
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356 <th>3-0</th> |
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357 </tr> |
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358 <tr> |
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359 <td>Destination register</td> |
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360 <td>Source A register</td> |
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361 <td>Source B register</td> |
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362 <td>$8</th> |
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363 </tr> |
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364 </table> |
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365 </p> |
39 | 366 <h4 id="or">or rA, rB, rD</h4> |
367 <p> | |
368 Bitwise or of rA and rB is stored in rD. | |
369 </p> | |
370 <p> | |
371 <strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero | |
372 </p> | |
42
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373 <p> |
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374 <strong>Encoding:</strong> |
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375 <table> |
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376 <tr> |
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377 <th>15-12</th> |
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378 <th>11-8</th> |
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379 <th>7-4</th> |
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380 <th>3-0</th> |
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381 </tr> |
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382 <tr> |
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383 <td>Destination register</td> |
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384 <td>Source A register</td> |
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385 <td>Source B register</td> |
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386 <td>$9</th> |
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387 </tr> |
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388 </table> |
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389 </p> |
39 | 390 <h4 id="xor">xor rA, rB, rD</h4> |
391 <p> | |
392 Bitwise exclusive or of rA and rB is stored in rD. | |
393 </p> | |
394 <p> | |
395 <strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero | |
396 </p> | |
42
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397 <p> |
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398 <strong>Encoding:</strong> |
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399 <table> |
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400 <tr> |
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401 <th>15-12</th> |
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402 <th>11-8</th> |
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403 <th>7-4</th> |
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404 <th>3-0</th> |
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405 </tr> |
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406 <tr> |
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407 <td>Destination register</td> |
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408 <td>Source A register</td> |
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409 <td>Source B register</td> |
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410 <td>$A</th> |
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411 </tr> |
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412 </table> |
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413 </p> |
39 | 414 <h4 id="lsl">lsl rA, rB, rD</h4> |
415 <p> | |
416 The value in rA is shifted left by rB bits and stored in rD | |
417 </p> | |
418 <p> | |
419 <strong>Flags:</strong> C = last bit shifted out of rA, N = result is negative, Z = result is zero | |
420 </p> | |
42
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421 <p> |
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422 <strong>Encoding:</strong> |
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423 <table> |
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424 <tr> |
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425 <th>15-12</th> |
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426 <th>11-8</th> |
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427 <th>7-4</th> |
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428 <th>3-0</th> |
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429 </tr> |
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430 <tr> |
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431 <td>Destination register</td> |
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432 <td>Source A register</td> |
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433 <td>Source B register</td> |
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434 <td>$B</th> |
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435 </tr> |
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436 </table> |
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437 </p> |
39 | 438 <h4 id="lsr">lsr rA, rB, rD</h4> |
439 <p> | |
440 The value in rA is shifted right by rB bits and stored in rD | |
441 </p> | |
442 <p> | |
443 <strong>Flags:</strong> C = last bit shifted out of rA, N = result is negative, Z = result is zero | |
444 </p> | |
42
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445 <p> |
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446 <strong>Encoding:</strong> |
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447 <table> |
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448 <tr> |
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449 <th>15-12</th> |
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450 <th>11-8</th> |
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451 <th>7-4</th> |
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452 <th>3-0</th> |
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453 </tr> |
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454 <tr> |
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455 <td>Destination register</td> |
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456 <td>Source A register</td> |
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457 <td>Source B register</td> |
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458 <td>$C</th> |
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459 </tr> |
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460 </table> |
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461 </p> |
39 | 462 <h4 id="asr">asr rA, rB, rD</h4> |
463 <p> | |
464 The value in rA is arithmetically shifted right by rB bits and stored in rD. The most significant bit of rA is copied | |
465 into the newly shifted bits. This allows asr to be used for signed division by powers of 2 as the sign is preserved. | |
466 </p> | |
40
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467 <p> |
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468 <strong>Flags:</strong> C = last bit shifted out of rA, N = result is negative, Z = result is zero |
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469 </p> |
42
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470 <p> |
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471 <strong>Encoding:</strong> |
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472 <table> |
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473 <tr> |
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474 <th>15-12</th> |
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475 <th>11-8</th> |
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476 <th>7-4</th> |
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477 <th>3-0</th> |
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478 </tr> |
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479 <tr> |
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480 <td>Destination register</td> |
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481 <td>Source A register</td> |
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482 <td>Source B register</td> |
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483 <td>$D</th> |
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484 </tr> |
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485 </table> |
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486 </p> |
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487 <h4 id="bcc">bCC LABEL</h4> |
39 | 488 <p> |
489 bCC performs a relative branch if the condition indicated by CC is true. It has a range of 131 instructions forward or | |
490 124 instructions backwards. CC must be one of the following values | |
491 <table> | |
492 <tr> | |
493 <th>CC</th> | |
494 <th>Mnemonic</th> | |
495 <th>Name</th> | |
496 <th>Description</th> | |
497 </tr> | |
498 <tr> | |
499 <td>0</td> | |
500 <td>ra</td> | |
501 <td>bRanch Always</td> | |
502 <td>Unconditionall branch</td> | |
503 </tr> | |
504 <tr> | |
505 <td>1</td> | |
506 <td>rf</td> | |
507 <td>bRanch False</td> | |
508 <td>Effectively a nop</td> | |
509 </tr> | |
510 <tr> | |
511 <td>2</td> | |
512 <td>eq</td> | |
513 <td>EQual</td> | |
514 <td>Branch if zero flag is 1</td> | |
515 </tr> | |
516 <tr> | |
517 <td>3</td> | |
518 <td>ne</td> | |
519 <td>Not Equal</td> | |
520 <td>Branch if zero flag is 0</td> | |
521 </tr> | |
522 <tr> | |
523 <td>4</td> | |
524 <td>mi</td> | |
525 <td>MInus</td> | |
526 <td>Branch if negative flag is 1</td> | |
527 </tr> | |
528 <tr> | |
529 <td>5</td> | |
530 <td>pl</td> | |
531 <td>PLus</td> | |
532 <td>Branch if negative flag is 0</td> | |
533 </tr> | |
534 <tr> | |
535 <td>6</td> | |
536 <td>cs</td> | |
537 <td>Carry Set</td> | |
538 <td>Branch if carry flag is 1. Unsigned "less than" when used with cmp</td> | |
539 </tr> | |
540 <tr> | |
541 <td>7</td> | |
542 <td>cc</td> | |
543 <td>Carry Clear</td> | |
544 <td>Branch if carry flag is 1. Unsigned "greater or equal" when used with cmp</td> | |
545 </tr> | |
546 <tr> | |
547 <td>8</td> | |
548 <td>gr</td> | |
549 <td>Greater</td> | |
550 <td>Branch if carry flag is 0 and the zero flag is zero. Unsigned "greater" when used with cmp</td> | |
551 </tr> | |
552 <tr> | |
553 <td>9</td> | |
554 <td>le</td> | |
555 <td>Less or Equal</td> | |
556 <td>Branch if carry flag is 1 or the zero flag is 1. Unsigned "lesser or equal" when used with cmp</td> | |
557 </tr> | |
558 </table> | |
559 Use of CC values greater than 9 will result in an invalid instruction exception. | |
560 </p> | |
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561 <p> |
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562 <strong>Flags:</strong> No change |
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563 </p> |
42
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
564 |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
565 <p> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
566 <strong>Encoding:</strong> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
567 <table> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
568 <tr> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
569 <th>15-12</th> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
570 <th>11-4</th> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
571 <th>3-0</th> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
572 </tr> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
573 <tr> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
574 <td>CC</td> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
575 <td>Signed 8-bit offset. Offset is multiplied by two before being added to PC</td> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
576 <td>$E</th> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
577 </tr> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
578 </table> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
579 </p> |
39 | 580 <h4 id="mov">mov rA, rD</h4> |
581 <p> | |
582 Stores the value of rA in rD. This can be used as a return or jump instruction if rD is PC. | |
583 </p> | |
40
413e7b9c0db1
Added flag change documentation for all instructions. Added hyperlinks to individual instructions. Added overviews for all the peripherals
Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
584 <p> |
413e7b9c0db1
Added flag change documentation for all instructions. Added hyperlinks to individual instructions. Added overviews for all the peripherals
Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
585 <strong>Flags:</strong> No change |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
586 </p> |
42
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
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|
587 <p> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
588 <strong>Encoding:</strong> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
589 <table> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
590 <tr> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
591 <th>15-12</th> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
592 <th>11-8</th> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
593 <th>7-4</th> |
a64e11e48a41
Added encoding for a bunch of instructions
Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
594 <th>3-0</th> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
595 </tr> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
596 <tr> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
597 <td>Destination register</td> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
598 <td>Source A register</td> |
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parents:
40
diff
changeset
|
599 <td>$0</td> |
a64e11e48a41
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parents:
40
diff
changeset
|
600 <td>$F</th> |
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parents:
40
diff
changeset
|
601 </tr> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
602 </table> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
603 </p> |
39 | 604 <h4 id="neg">neg rA, rD</h4> |
605 <p> | |
606 Calculates the 2s complement of rA and stores it in rD. This can be used in combination with add to implement subtraction. | |
607 </p> | |
40
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
608 <p> |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
609 <strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
610 </p> |
42
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
611 <p> |
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
612 <strong>Encoding:</strong> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
613 <table> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
614 <tr> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
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|
615 <th>15-12</th> |
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
616 <th>11-8</th> |
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40
diff
changeset
|
617 <th>7-4</th> |
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parents:
40
diff
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|
618 <th>3-0</th> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
619 </tr> |
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
620 <tr> |
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40
diff
changeset
|
621 <td>Destination register</td> |
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parents:
40
diff
changeset
|
622 <td>Source A register</td> |
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parents:
40
diff
changeset
|
623 <td>$1</td> |
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parents:
40
diff
changeset
|
624 <td>$F</th> |
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parents:
40
diff
changeset
|
625 </tr> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
626 </table> |
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parents:
40
diff
changeset
|
627 </p> |
39 | 628 <h4 id="not">not rA, rD</h4> |
629 <p> | |
630 Calculates the 1s complement of rA and stores it in rD. | |
631 </p> | |
40
413e7b9c0db1
Added flag change documentation for all instructions. Added hyperlinks to individual instructions. Added overviews for all the peripherals
Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
632 <p> |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
633 <strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
634 </p> |
42
a64e11e48a41
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diff
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|
635 <p> |
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
636 <strong>Encoding:</strong> |
a64e11e48a41
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40
diff
changeset
|
637 <table> |
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40
diff
changeset
|
638 <tr> |
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parents:
40
diff
changeset
|
639 <th>15-12</th> |
a64e11e48a41
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parents:
40
diff
changeset
|
640 <th>11-8</th> |
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parents:
40
diff
changeset
|
641 <th>7-4</th> |
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parents:
40
diff
changeset
|
642 <th>3-0</th> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
643 </tr> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
644 <tr> |
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
645 <td>Destination register</td> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
646 <td>Source A register</td> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
647 <td>$2</td> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
648 <td>$F</th> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
649 </tr> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
650 </table> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
651 </p> |
39 | 652 <h4 id="cmp">cmp rA, rD</h4> |
653 <p> | |
654 Subtracts rA from rD and discards the result, but still updates flags. | |
655 </p> | |
40
413e7b9c0db1
Added flag change documentation for all instructions. Added hyperlinks to individual instructions. Added overviews for all the peripherals
Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
656 <p> |
413e7b9c0db1
Added flag change documentation for all instructions. Added hyperlinks to individual instructions. Added overviews for all the peripherals
Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
657 <strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
658 </p> |
42
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
659 <p> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
660 <strong>Encoding:</strong> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
661 <table> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
662 <tr> |
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40
diff
changeset
|
663 <th>15-12</th> |
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parents:
40
diff
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|
664 <th>11-8</th> |
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40
diff
changeset
|
665 <th>7-4</th> |
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parents:
40
diff
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|
666 <th>3-0</th> |
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parents:
40
diff
changeset
|
667 </tr> |
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
668 <tr> |
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Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
669 <td>Destination register</td> |
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40
diff
changeset
|
670 <td>Source A register</td> |
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parents:
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diff
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|
671 <td>$3</td> |
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parents:
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diff
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|
672 <td>$F</th> |
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
673 </tr> |
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
674 </table> |
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
675 </p> |
39 | 676 <h4 id="call">call rA, rD</h4> |
677 <p> | |
678 Stores the address of the next instruction in rD and sets PC to the value in rA. Used for calling subroutines. | |
679 </p> | |
40
413e7b9c0db1
Added flag change documentation for all instructions. Added hyperlinks to individual instructions. Added overviews for all the peripherals
Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
680 <p> |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
681 <strong>Flags:</strong> No change |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
682 </p> |
42
a64e11e48a41
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parents:
40
diff
changeset
|
683 <p> |
a64e11e48a41
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parents:
40
diff
changeset
|
684 <strong>Encoding:</strong> |
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parents:
40
diff
changeset
|
685 <table> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
686 <tr> |
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parents:
40
diff
changeset
|
687 <th>15-12</th> |
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parents:
40
diff
changeset
|
688 <th>11-8</th> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
689 <th>7-4</th> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
690 <th>3-0</th> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
691 </tr> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
692 <tr> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
693 <td>Destination register</td> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
694 <td>Source A register</td> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
695 <td>$4</td> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
696 <td>$F</th> |
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
697 </tr> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
698 </table> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
699 </p> |
39 | 700 <h4 id="swap">swap rA, rD</h4> |
701 <p> | |
702 Swaps the values in rA and rD. | |
703 </p> | |
40
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
704 <p> |
413e7b9c0db1
Added flag change documentation for all instructions. Added hyperlinks to individual instructions. Added overviews for all the peripherals
Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
705 <strong>Flags:</strong> No change |
413e7b9c0db1
Added flag change documentation for all instructions. Added hyperlinks to individual instructions. Added overviews for all the peripherals
Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
706 </p> |
42
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
parents:
40
diff
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|
707 <p> |
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
708 <strong>Encoding:</strong> |
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
709 <table> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
710 <tr> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
711 <th>15-12</th> |
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Michael Pavone <pavone@retrodev.com>
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40
diff
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|
712 <th>11-8</th> |
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40
diff
changeset
|
713 <th>7-4</th> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
714 <th>3-0</th> |
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
715 </tr> |
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
716 <tr> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
717 <td>Destination register</td> |
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
718 <td>Source A register</td> |
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40
diff
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|
719 <td>$5</td> |
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
720 <td>$F</th> |
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
721 </tr> |
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
722 </table> |
a64e11e48a41
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Michael Pavone <pavone@retrodev.com>
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40
diff
changeset
|
723 </p> |
45
5338b9affd09
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Michael Pavone <pavone@retrodev.com>
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42
diff
changeset
|
724 <h4 id="longjmp">longjmp rA, rD</h4> |
39 | 725 <p> |
45
5338b9affd09
Updated HTML documentation to reflect CPU changes
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42
diff
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|
726 Sets PC to rA and PCH to the low 7-bits of rD |
39 | 727 </p> |
40
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
728 <p> |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
729 <strong>Flags:</strong> No change |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
730 </p> |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
731 <p> |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
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|
732 <strong>Flags:</strong> No change |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
733 </p> |
39 | 734 <h4 id="ini">ini IM, rD</h4> |
735 <p> | |
736 Reads a word from the IO port indicated by IM and stores it in rD. IM can range from 0 to 15. | |
737 </p> | |
40
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
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|
738 <p> |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
739 <strong>Flags:</strong> No change |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
740 </p> |
39 | 741 <h4 id="outi">outi</h4> |
742 <p> | |
743 Writes the word stored in rD to the IO port indicated by IM. IM can range from 0 to 15. | |
744 </p> | |
40
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
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|
745 <p> |
413e7b9c0db1
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39
diff
changeset
|
746 <strong>Flags:</strong> No change |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
747 </p> |
39 | 748 <h4 id="addi">addi IM, rD</h4> |
749 <p> | |
750 Adds IM to the value in rD and stores the result in rD. IM range from -8 to -1 or 1 to 8. A value of 0 is used to indicate 8. | |
751 </p> | |
40
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
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|
752 <p> |
413e7b9c0db1
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39
diff
changeset
|
753 <strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
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|
754 </p> |
39 | 755 <h4 id="andi">andi IM, rD</h4> |
756 <p> | |
45
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42
diff
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|
757 Performs a bitwise and of IM and the value in rD and stores the result in rD. IM can range from -8 to -1 or 1 to 8. A value of 0 is used to indicate 8. |
39 | 758 </p> |
40
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
759 <p> |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
760 <strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
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|
761 </p> |
39 | 762 <h4 id="ori">ori IM, rD</h4> |
763 <p> | |
45
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42
diff
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|
764 Performs a bitwise or of IM and the value in rD and stores the result in rD. IM can range from -8 to -1 or 1 to 8. A value of 0 is used to indicate 8. |
5338b9affd09
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Michael Pavone <pavone@retrodev.com>
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42
diff
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|
765 </p> |
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Michael Pavone <pavone@retrodev.com>
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42
diff
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|
766 <h4 id="ori">xori IM, rD</h4> |
5338b9affd09
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Michael Pavone <pavone@retrodev.com>
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42
diff
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|
767 <p> |
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Michael Pavone <pavone@retrodev.com>
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42
diff
changeset
|
768 Performs a bitwise exclusive or of IM and the value in rD and stores the result in rD. IM can range from -8 to -1 or 1 to 8. A value of 0 is used to indicate 8. |
39 | 769 </p> |
40
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
770 <p> |
413e7b9c0db1
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parents:
39
diff
changeset
|
771 <strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
772 </p> |
39 | 773 <h4 id="lsli">lsli IM, rD</h4> |
774 <p> | |
775 Shifts the value in rD IM bits to the left. IM can range from 1 to 8. | |
776 </p> | |
40
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
777 <p> |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
778 <strong>Flags:</strong> C = last bit shifted out of rA, N = result is negative, Z = result is zero |
413e7b9c0db1
Added flag change documentation for all instructions. Added hyperlinks to individual instructions. Added overviews for all the peripherals
Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
779 </p> |
39 | 780 <h4 id="lsri">lsri IM, rD</h4> |
781 <p> | |
782 Shifts the value in rD IM bits to the right. IM can range from 1 to 8. | |
783 </p> | |
40
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
784 <p> |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
785 <strong>Flags:</strong> C = last bit shifted out of rA, N = result is negative, Z = result is zero |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
786 </p> |
39 | 787 <h4 id="cmpi">cmpi IM, rd</h4> |
788 <p> | |
789 Subtracts IM from rD and discards the result, but updates flags. IM can range from -8 to 7. | |
790 </p> | |
40
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
791 <p> |
413e7b9c0db1
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39
diff
changeset
|
792 <strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
793 </p> |
39 | 794 <h4 id="reti">reti rD</h4> |
795 <p> | |
796 Sets rD to the value storeed in EUR, SR to the value stored in ESR and PC to the value stored in EPC. This instruction is used for returning from an | |
797 exception or interrupt. | |
798 </p> | |
40
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
799 <p> |
413e7b9c0db1
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39
diff
changeset
|
800 <strong>Flags:</strong> Updated corresponding to the value in ESR. |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
801 </p> |
39 | 802 <h4 id="trapi">trapi IM</h4> |
803 <p> | |
40
413e7b9c0db1
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39
diff
changeset
|
804 Causes an exception to be taken to the vector indicated by IM |
413e7b9c0db1
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39
diff
changeset
|
805 </p> |
49
5f30c4d18d79
Updated the HTML documentation a bit
Michael Pavone <pavone@retrodev.com>
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45
diff
changeset
|
806 <h4 id="push">push rD</h4> |
40
413e7b9c0db1
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39
diff
changeset
|
807 <p> |
49
5f30c4d18d79
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diff
changeset
|
808 Pushes the value in register rD onto the stack. |
5f30c4d18d79
Updated the HTML documentation a bit
Michael Pavone <pavone@retrodev.com>
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45
diff
changeset
|
809 </p> |
5f30c4d18d79
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Michael Pavone <pavone@retrodev.com>
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45
diff
changeset
|
810 <p> |
5f30c4d18d79
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Michael Pavone <pavone@retrodev.com>
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45
diff
changeset
|
811 <strong>Flags:</strong> Condition code flags unchanged. |
5f30c4d18d79
Updated the HTML documentation a bit
Michael Pavone <pavone@retrodev.com>
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45
diff
changeset
|
812 </p> |
5f30c4d18d79
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Michael Pavone <pavone@retrodev.com>
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45
diff
changeset
|
813 <hr id="pop">pop rD</h4> |
5f30c4d18d79
Updated the HTML documentation a bit
Michael Pavone <pavone@retrodev.com>
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45
diff
changeset
|
814 <p> |
5f30c4d18d79
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45
diff
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|
815 Pops a value of the stack and stores it in rD |
5f30c4d18d79
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Michael Pavone <pavone@retrodev.com>
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45
diff
changeset
|
816 </p> |
5f30c4d18d79
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Michael Pavone <pavone@retrodev.com>
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45
diff
changeset
|
817 <p> |
5f30c4d18d79
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diff
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|
818 <strong>Flags:</strong> Condition code flags unchanged. |
39 | 819 </p> |
820 <h4 id="getepc">getepc rD</h4> | |
821 <p> | |
822 Stores the value of EPC in rD. | |
823 </p> | |
40
413e7b9c0db1
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39
diff
changeset
|
824 <p> |
413e7b9c0db1
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39
diff
changeset
|
825 <strong>Flags:</strong> No change |
413e7b9c0db1
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39
diff
changeset
|
826 </p> |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
827 <h4 id="setepc">setepc rD</h4> |
39 | 828 <p> |
829 Stores the vaule of rD in EPC. | |
830 </p> | |
831 <p> | |
40
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
832 <strong>Flags:</strong> No change |
413e7b9c0db1
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39
diff
changeset
|
833 </p> |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
834 <h4 id="getesr">getesr rD</h4> |
413e7b9c0db1
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39
diff
changeset
|
835 <p> |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
836 Stores the value of ESR in rD. |
39 | 837 </p> |
838 <p> | |
40
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
839 <strong>Flags:</strong> No change |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
840 </p> |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
841 <h4 id="setesr">setesr rD</h4> |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
842 <p> |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
843 Stores the value of rD in ESR. |
39 | 844 </p> |
845 <p> | |
40
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
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39
diff
changeset
|
846 <strong>Flags:</strong> No change |
413e7b9c0db1
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39
diff
changeset
|
847 </p> |
413e7b9c0db1
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39
diff
changeset
|
848 <h4 id="geteur">geteur rD</h4> |
413e7b9c0db1
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39
diff
changeset
|
849 <p> |
413e7b9c0db1
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39
diff
changeset
|
850 Stores the value of EUR in rD. |
39 | 851 </p> |
852 <p> | |
40
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
853 <strong>Flags:</strong> No change |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
854 </p> |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
855 <h4 id="seteur">seteur rD</h4> |
413e7b9c0db1
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Michael Pavone <pavone@retrodev.com>
parents:
39
diff
changeset
|
856 <p> |
413e7b9c0db1
Added flag change documentation for all instructions. Added hyperlinks to individual instructions. Added overviews for all the peripherals
Michael Pavone <pavone@retrodev.com>
parents:
39
diff
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|
857 Stores the value of rd in EUR. |
39 | 858 </p> |
859 <p> | |
40
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860 <strong>Flags:</strong> No change |
413e7b9c0db1
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861 </p> |
413e7b9c0db1
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diff
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862 <h4 id="getenum">getenum rD</h4> |
413e7b9c0db1
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863 <p> |
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864 Stores the value of ENUM in rD. |
39 | 865 </p> |
866 <p> | |
40
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867 <strong>Flags:</strong> No change |
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|
868 </p> |
413e7b9c0db1
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869 <h4 id="setenum">setenum rD</h4> |
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|
870 <p> |
413e7b9c0db1
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871 Stores the value of rd in ENUM. |
39 | 872 </p> |
873 <p> | |
40
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|
874 <strong>Flags:</strong> No change |
413e7b9c0db1
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diff
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|
875 </p> |
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876 <h4 id="getvbr">getvbr rD</h4> |
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diff
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|
877 <p> |
413e7b9c0db1
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diff
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|
878 Stores the value of VBR in rD. |
39 | 879 </p> |
40
413e7b9c0db1
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diff
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|
880 <p> |
413e7b9c0db1
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diff
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|
881 <strong>Flags:</strong> No change |
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882 </p> |
413e7b9c0db1
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diff
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|
883 <h4 id="setvbr">setvbr rD</h4> |
39 | 884 <p> |
40
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885 Stores the valueof rD in VBR. |
413e7b9c0db1
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|
886 </p> |
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|
887 <p> |
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diff
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888 <strong>Flags:</strong> No change |
39 | 889 </p> |
890 <h2 id="video">Video</h2> | |
40
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|
891 <h3 id="vidover">Overview</h3> |
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diff
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|
892 <p> |
49
5f30c4d18d79
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893 Simple 16 features a simple linear framebuffer using indexed color. There is 128KB of VRAM arranged as two 64KB framebuffers. At any given time one buffer is used for |
5f30c4d18d79
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894 display and the other is accessible to the CPU. Both 4bpp and 8bpp depths are available. The resolution of the display is fixed at 320x240, but up to 31 lines can be |
5f30c4d18d79
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895 blanked at the top and bottom of the display to save on VRAM usage or to implement a letterbox effect. |
40
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|
896 </p> |
39 | 897 <h2 id="audio">Audio</h2> |
40
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898 <h3 id="audover">Overview</h3> |
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|
899 <p> |
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900 Simple 16 has four square-wave tone generators with a 16-bit period and an 8-bit volume. The special value of 0 for the period causes the volume to be output constantly |
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901 allowing the volume register to be used as a simple 8-bit DAC. |
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|
902 </p> |
39 | 903 <h2 id="timer">Timer</h2> |
40
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|
904 <h3 id="timeover">Overview</h3> |
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905 <p> |
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|
906 Simple 16 has a single timer with a 16-bit period. Interrupt 0 is triggered on timer expiration. |
413e7b9c0db1
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|
907 </p> |
39 | 908 <h2 id="controllers">Controllers</h2> |
40
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|
909 <h3 id="contover">Overview</h3> |
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|
910 <p> |
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911 Simple 16 supports 2 controllers, each with a D-pad and 8 buttons configured in either an SNES (4 action buttons on the face + 2 shoulder buttons + Start and Select) |
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|
912 or Genesis 6-button controller (6 action buttons on the face + Start and Mode) arrangement. In this document, the buttons are given using the Genesis naming scheme. |
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|
913 For a controller following the SNES layout, the right trigger is 'C', the left trigger is 'Z' and 'Select' is 'Mode'. |
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|
914 </p> |
39 | 915 <h2 id="serial">Serial Port</h2> |
40
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|
916 <h3>Overview</h3> |
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|
917 <p> |
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|
918 This port can be thought of a simple UART for debugging purposes. In an emulator, a write should result in a byte being written to stdout and a read should return |
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diff
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|
919 a byte read from stdin. This peripheral can be omitted in which case writes should be ignored and reads should return $FFFF. The primary purpose of this port is |
413e7b9c0db1
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39
diff
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|
920 to enable easy debugging of the CPU core before other, more complicated, peripherals are working. |
39 | 921 <h2 id="cart">Cartridge</h2> |
40
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|
922 <h3>Overview</h3> |
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|
923 <p> |
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|
924 Simple 16 allows for 48KB of flat mapped cartridge ROM. Future revisions may allow banking. |
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|
925 </p> |
39 | 926 </body> |
927 </html> |