Mercurial > repos > simple16

comparison simple_console.txt @ 43:6e7bfe83d2b0

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
author Michael Pavone <pavone@retrodev.com>
date Sat, 27 Aug 2016 22:38:31 -0700
parents 351a0d0cce3b
children 51672bd41cdd
comparison
equal deleted inserted replaced
42:a64e11e48a41 43:6e7bfe83d2b0
41 3: cmp 41 3: cmp
42 4: call 42 4: call
43 A = register containing pointer to function 43 A = register containing pointer to function
44 D = register that will store PC value 44 D = register that will store PC value
45 5: swap 45 5: swap
46 6: in 46 6: longjmp
47 7: out 47 A = register containing pointer to function
48 8: ini 48 D = register containing new code segment value
49 9: outi 49 7: ini
50 A: addi 50 8: outi
51 B: andi 51 9: addi
52 C: ori 52 A: andi
53 B: ori
54 C: xori
53 D: ls[lr]i 55 D: ls[lr]i
54 MSB of AAAA determines direction 56 MSB of AAAA determines direction
55 LS 3 bits determines magnitude 57 LS 3 bits determines magnitude
56 E: cmpi 58 E: cmpi
57 F: single reg 59 F: single reg
58 60
59 61
60 DDDD OOOO 1111 1111 62 DDDD OOOO 1111 1111
61 63
62 0: reti - return from interrupt, D = register to restore from uer 64 0: reti - return from interrupt, D = register to restore from uer
63 1: trap 65 1: trapi
64 2: trapi 66 2: getepc
65 3: getepc 67 3: setepc
66 4: setepc 68 4: getepch
67 5: getesr 69 5: setepch
68 6: setesr 70 6: getesr
69 7: getenum 71 7: setesr
70 8: setenum 72 8: getenum
71 9: getuer 73 9: setenum
72 A: setuer 74 A: getuer
73 B: invalid 75 B: setuer
74 C: invalid 76 C: getvbr
75 D: invalid 77 D: setvbr
76 E: invalid 78 E: getdatabanks
77 F: invalid 79 F: setdatabanks
78 80
79 81
80 Registers: 82 Registers:
81 83
82 r0 - r12 : general purpose 84 r0 - r12 : general purpose
84 r14 : PC 86 r14 : PC
85 r15 : status register 87 r15 : status register
86 88
87 Special Registers 89 Special Registers
88 epc - Exception PC - Stores PC value to resume to when entering an exception handler 90 epc - Exception PC - Stores PC value to resume to when entering an exception handler
91 epch - High 7-bits of PC
89 esr - Exception SR - same as above, but for SR 92 esr - Exception SR - same as above, but for SR
90 eur - Exceptuion User Reg - reg for temporary storage of a reg in a handler, intended to be used for the stack pointer 93 eur - Exceptuion User Reg - reg for temporary storage of a reg in a handler, intended to be used for the stack pointer
91 enum - Exception Number - holds the number of the most recent exception 94 enum - Exception Number - holds the number of the most recent exception
95 databanks - Holds the upper bytes used for data accesses (MSB = byte for upper half of memory space, LSB = byte for lower half of memory space)
92 96
93 IO: Ports 97 IO: Ports
94 98
95 0: Controller 1 99 0: Controller 1
96 1: Controller 2 100 1: Controller 2
99 103
100 4: Channel A Freq 104 4: Channel A Freq
101 Load value for a 16-bit down-counter 105 Load value for a 16-bit down-counter
102 Polarity of output is switched on transition from 1 to 0 106 Polarity of output is switched on transition from 1 to 0
103 Value is loaded on cycles where counter is 0 107 Value is loaded on cycles where counter is 0
104 Special case value of 0 in this register forces polarity to positive 108 Special case value of 0 in this register forces polarity to positive, useful for PCM playback
105 5: Channel B Freq 109 5: Channel B Freq
106 6: Channel C Freq 110 6: Channel C Freq
107 7: Channel D Freq 111 7: Channel D Freq
108 112
109 8: Channel A/B Vol 113 8: Channel A/B Vol
110 9: Channel C/D Vol 114 9: Channel C/D Vol
111 115
112 A: Timer Freq 116 A: Timer Freq
113 B: "Serial" Debug Port 117 B: "Serial" Debug Port
114 118
115 C: Write Vertical Scroll : Read Vertical Position 119 C: Framebuffer start offset : Read Vertical Position
116 MMMM MCCC CCCC CFFF 120 D: Graphics mode : Read Horizontal Position
117 C = coarse scroll bit 121 EDVP PSSS SSEE EEEF
118 F = fine scroll bit 122 E = 0 display disabled, 1 display enabled
119 M = mask bit 123 D = 0 4 bpp, 1 8bpp
120 controls which bits come directly from register 124 F = 0 front buffer is lower 64K, 1 front buffer is upper 64K
121 and which bits come from the sum of the register 125 P = palette select
122 and the current line number 126 S = blanked lines at start of frame
123 127 E = blanked lines at end of frame
124 D: Write Horizontal Scroll : Read Horizontal Position 128 E: CRAM update port : Read Status
125 xxxx xxxC CCCC CFFF 129 1st write determines destination and length
126 C = coarse scroll bit 130 DDDD DDDD LLLL LLLL
127 F = fine scroll bit 131 Next L writes are written to D and subsequent addresses
128 x = unused 132
129 E: Write Dest Address : Read Status 133 F: Reserved
130 F: Write Data : Read ???
131 134
132 135
133 Name Table Start Address: 136 Video Hardware:
134 0VVV VVVV VHHH HHH0 137 128KB of VRAM organized into two 64KB linear framebuffers
138 Pixels are 4bpp or 8bbp in chunky format
139 256 words of 16-bit CRAM
140 In 4bpp mode, P field of graphics mode selects one of 4, 16 color palettes
141 S and E fields of mode allow hardware letter boxing, effectively increasing the length of vblank
142 F field selects which 64KB framebuffer is used for the active display
143 Active buffer is inaccessible to CPU, but CPU has free reign over inactive buffer
144 H-Counter goes from 0-415 and then wraps back to zero
145 V-Counter goes from 0-261 and then wraps back to zero
146 V-Counter increments when H-Counter wraps
135 147
136 V = Coarse scroll bit from vertical scroll value 148 Memory Map
137 H = Coarse scroll bit from horizontal scroll value 149 23-bit address space
138 150 $0 - $3FFFFF - ROM
139 VDP Memory Map 151 $400000 - $4FFFFF - 128K RAM, mirrored every 128KB
140 0000 - 7FFF = Pattern/Name Table RAM 152 $500000 - $6FFFFF - Reserved
141 8000 - FDFF = unused, returns $FFFF 153 $700000 - $7FFFFF - 64KB VRAM back buffer, mirrored every 64KB
142 FE00 - FEFF = Sprite RAM
143 FF00 - FF7F = Palette RAM
144 FF80 - FFFF = Palette RAM (mirror)
145 154
146 Another View -
147 MSB determines whether destination is main RAM
148 For MSB 1
149 Next 7 MSB determines which special RAM is the destination
150 Only values of 7E and 7F are valid for these bits at present
151 8 LSB determine offset (1 LSB ignored)
152
153 Writing to Data port puts value into a one word FIFO
154 Offset within memory type is increment when word is pulled from FIFO
155 Writing to the FIFO when it is full will cause the existing entry to be overwritten
156
157
158 Pattern Format:
159 4bpp in an 8x8 tile arrangement
160
161
162 Sprite Table Entry:
163
164 XXXXXXXX YYYYYYYY
165 IXPVHSNN NNNNNNNN
166
167 S: size -- 0 = 8x8, 1 = 16x16
168 P: Palette selector
169 H: Horizontal flip
170 V: Vertical flip
171 I: Priority
172 N: Name
173 X: X position (left of screen = 16, right of screen = ?)
174 Y: Y position (top of screen = 16, bottom of screen = 240)
175
176
177 Name Table Entry:
178
179 IPPVHxNN NNNNNNNN
180
181 P: Palette selector
182 H: Horizontal flip
183 V: Vertical flip
184 I: Priority
185 N: Name
186 x: Unused, should be set to 0
187 155
188 26.112 MHZ Clock 156 26.112 MHZ Clock
189 Dot Clock Divider 4 157 Dot Clock Divider 4
190 CPU Clock Divider 20 (assuming 1 cycle/instruction, 5 for 4 cycles/instruction) 158 CPU Clock Divider 4 (assuming 1 cycle/instruction, 1 for 4 cycles/instruction)
191 Audio Timer Divider 34 159 Audio Timer Divider 34
192 Audio Output Divider 544 160 Audio Output Divider 544
193 Interrupt Timer Divider 32 161 Interrupt Timer Divider 32
194 162
195 Alternatively 13.056 Mhz clock and cut the dividers in half 163 Alternatively 13.056 Mhz clock and cut the dividers in half
196 164
197 165
198
199 H-Counter goes from 0-415 and then wraps back to zero
200 V-Counter goes from 0-261 and then wraps back to zero
201 V-Counter increments when H-Counter wraps
202
203 Rendering Process:
204 208 main VRAM access slots
205 123 slots for background
206 160-123 = 37 extra slots during active display
207 48 slots during inactive display
208 80 slots for sprite rendering
209 5 slots remain for refresh or external access
210
211 Since sprite rendering needs to intrude on active display period,
212 a double buffered line buffer is needed. Useful for VGA compatibility anyway
213