Mercurial > repos > simple16
comparison simple_console.txt @ 0:7e44f7d5810b
Initial commit. CPU working well enough for simple hello world program.
author | Michael Pavone <pavone@retrodev.com> |
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date | Tue, 22 Mar 2016 22:44:02 -0700 |
parents | |
children | 6204c81e2933 |
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-1:000000000000 | 0:7e44f7d5810b |
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1 Key: | |
2 1 = literal 1 bit | |
3 0 = literal 0 bit | |
4 O = opcode bit | |
5 D = destination register bit | |
6 A = source A register bit | |
7 B = source B register bit | |
8 | |
9 DDDD AAAA BBBB OOOO | |
10 | |
11 0: ldim | |
12 D = destination reg | |
13 A and B form 8-bit immediate value | |
14 1: ldimh | |
15 D = destination reg | |
16 A and B form 8-bit immediate value | |
17 2: ld8 | |
18 3: ld16 | |
19 4: str8 | |
20 5: str16 | |
21 6: add | |
22 7: adc | |
23 8: and | |
24 9: or | |
25 A: xor | |
26 B: lsl | |
27 C: lsr | |
28 D: asr | |
29 E: bcc | |
30 F: single source | |
31 | |
32 | |
33 | |
34 DDDD AAAA OOOO 1111 | |
35 | |
36 single source | |
37 | |
38 0: mov | |
39 1: neg | |
40 2: not | |
41 3: cmp | |
42 4: call | |
43 A = register containing pointer to function | |
44 D = register that will store PC value | |
45 5: swap | |
46 6: in | |
47 7: out | |
48 8: ini | |
49 9: outi | |
50 A: addi | |
51 B: andi | |
52 C: ori | |
53 D: ls[lr]i | |
54 MSB of AAAA determines direction | |
55 LS 3 bits determines magnitude | |
56 E: asri | |
57 F: single reg | |
58 | |
59 | |
60 DDDD OOOO 1111 1111 | |
61 | |
62 0: reti - return from interrupt, D = register to restore from uer | |
63 1: trap | |
64 2: trapi | |
65 3: getepc | |
66 4: setepc | |
67 5: getesr | |
68 6: setesr | |
69 7: getenum | |
70 8: setenum | |
71 9: getuer | |
72 A: setuer | |
73 B: getenum | |
74 C: setenum | |
75 E: invalid | |
76 F: invalid | |
77 | |
78 | |
79 Registers: | |
80 | |
81 r0 - r12 : general purpose | |
82 r13 : technically general purpose, but canonically the stack register | |
83 r14 : PC | |
84 r15 : status register | |
85 | |
86 IO: Ports | |
87 | |
88 0: Controller 1 | |
89 1: Controller 2 | |
90 2: Controller 3 | |
91 3: Controller 4 | |
92 | |
93 4: Channel A Freq | |
94 Load value for a 16-bit down-counter | |
95 Polarity of output is switched on transition from 1 to 0 | |
96 Value is loaded on cycles where counter is 0 | |
97 Special case value of 0 in this register forces polarity to positive | |
98 5: Channel B Freq | |
99 6: Channel C Freq | |
100 7: Channel D Freq | |
101 | |
102 8: Channel A/B Vol | |
103 9: Channel C/D Vol | |
104 | |
105 A: Timer Freq | |
106 B: "Serial" Debug Port | |
107 | |
108 D: Write Pallette Address : Read Vertical Position | |
109 E: Write Name Table Address : Read Horizontal Position | |
110 F: Write Sprite Table Address : Read Status? | |
111 | |
112 | |
113 | |
114 | |
115 |