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comparison simple_console.txt @ 4:8170d60f188b

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Added basic rendering timing outline and made some other minor spec changes
author Michael Pavone <pavone@retrodev.com>
date Fri, 25 Mar 2016 19:26:23 -0700
parents 08b69e3f9f17
children 18b66690ae13
comparison
equal deleted inserted replaced
3:08b69e3f9f17 4:8170d60f188b
124 xxxx xxxC CCCC CFFF 124 xxxx xxxC CCCC CFFF
125 C = coarse scroll bit 125 C = coarse scroll bit
126 F = fine scroll bit 126 F = fine scroll bit
127 x = unused 127 x = unused
128 E: Write Dest Address : Read Status 128 E: Write Dest Address : Read Status
129 F: Write Data : Read Data 129 F: Write Data : Read ???
130 130
131 131
132 Name Table Start Address: 132 Name Table Start Address:
133 0VVV VVVV VHHH HHH0 133 0VVV VVVV VHHH HHH0
134 134
147 For MSB 1 147 For MSB 1
148 Next 7 MSB determines which special RAM is the destination 148 Next 7 MSB determines which special RAM is the destination
149 Only values of 7E and 7F are valid for these bits at present 149 Only values of 7E and 7F are valid for these bits at present
150 8 LSB determine offset (1 LSB ignored) 150 8 LSB determine offset (1 LSB ignored)
151 151
152 Writing to Data port puts word into FIFO 152 Writing to Data port puts value into a one word FIFO
153 Offset within memory type is increment when word is pulled from FIFO 153 Offset within memory type is increment when word is pulled from FIFO
154 Writing to the FIFO when it is full will cause the existing entry to be overwritten
155
154 156
155 Pattern Format: 157 Pattern Format:
156 4bpp in an 8x8 tile arrangement 158 4bpp in an 8x8 tile arrangement
157 159
158 160
193 195
194 196
195 H-Counter goes from 0-415 and then wraps back to zero 197 H-Counter goes from 0-415 and then wraps back to zero
196 V-Counter goes from 0-261 and then wraps back to zero 198 V-Counter goes from 0-261 and then wraps back to zero
197 V-Counter increments when H-Counter wraps 199 V-Counter increments when H-Counter wraps
200
201 Rendering Process:
202 208 main VRAM access slots
203 123 slots for background
204 160-123 = 37 extra slots during active display
205 48 slots during inactive display
206 80 slots for sprite rendering
207 5 slots remain for refresh or external access
208
209 Since sprite rendering needs to intrude on active display period,
210 a double buffered line buffer is needed. Useful for VGA compatibility anyway
211