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Added encoding for a bunch of instructions
author Michael Pavone <pavone@retrodev.com>
date Mon, 11 Apr 2016 23:35:51 -0700
parents 413e7b9c0db1
children 5338b9affd09
comparison
equal deleted inserted replaced
41:23bea9b9569f 42:a64e11e48a41
145 ldim sign extends an 8-bit immediate value to 16-bits and assigns it to the designated register. 145 ldim sign extends an 8-bit immediate value to 16-bits and assigns it to the designated register.
146 </p> 146 </p>
147 <p> 147 <p>
148 <strong>Flags:</strong> No change 148 <strong>Flags:</strong> No change
149 </p> 149 </p>
150 <p>
151 <strong>Encoding:</strong>
152 <table>
153 <tr>
154 <th>15-12</th>
155 <th>11-4</th>
156 <th>3-0</th>
157 </tr>
158 <tr>
159 <td>Destination register</td>
160 <td>8-bit immediate value</td>
161 <td>$0</th>
162 </tr>
163 </table>
164 </p>
150 <h4 id="ldimh">lidmh IM, rD</h4> 165 <h4 id="ldimh">lidmh IM, rD</h4>
151 <p> 166 <p>
152 ldimh assigns an 8-bit immediate value to the upper 8-bits of rD. 167 ldimh assigns an 8-bit immediate value to the upper 8-bits of rD.
153 </p> 168 </p>
154 <p> 169 <p>
155 <strong>Flags:</strong> No change 170 <strong>Flags:</strong> No change
156 </p> 171 </p>
172 <p>
173 <strong>Encoding:</strong>
174 <table>
175 <tr>
176 <th>15-12</th>
177 <th>11-4</th>
178 <th>3-0</th>
179 </tr>
180 <tr>
181 <td>Destination register</td>
182 <td>8-bit immediate value</td>
183 <td>$1</th>
184 </tr>
185 </table>
186 </p>
157 <h4 id="ld8">ld8 rA, rB, rD</h4> 187 <h4 id="ld8">ld8 rA, rB, rD</h4>
158 <p> 188 <p>
159 Reads a byte from the address indicated by the sum of rA and rB and loads it into rD 189 Reads a byte from the address indicated by the sum of rA and rB and loads it into rD
160 </p> 190 </p>
161 <p> 191 <p>
162 <strong>Flags:</strong> No change 192 <strong>Flags:</strong> No change
163 </p> 193 </p>
194 <p>
195 <strong>Encoding:</strong>
196 <table>
197 <tr>
198 <th>15-12</th>
199 <th>11-8</th>
200 <th>7-4</th>
201 <th>3-0</th>
202 </tr>
203 <tr>
204 <td>Destination register</td>
205 <td>Source A register</td>
206 <td>Source B register</td>
207 <td>$2</th>
208 </tr>
209 </table>
210 </p>
164 <h4 id="ld16">ld16 rA, rB, rD</h4> 211 <h4 id="ld16">ld16 rA, rB, rD</h4>
165 <p> 212 <p>
166 Reads a word from the address indicated by the sum of rA and rB and loads it into rD 213 Reads a word from the address indicated by the sum of rA and rB and loads it into rD
167 </p> 214 </p>
168 <p> 215 <p>
169 <strong>Flags:</strong> No change 216 <strong>Flags:</strong> No change
170 </p> 217 </p>
218 <p>
219 <strong>Encoding:</strong>
220 <table>
221 <tr>
222 <th>15-12</th>
223 <th>11-8</th>
224 <th>7-4</th>
225 <th>3-0</th>
226 </tr>
227 <tr>
228 <td>Destination register</td>
229 <td>Source A register</td>
230 <td>Source B register</td>
231 <td>$3</th>
232 </tr>
233 </table>
234 </p>
171 <h4 id="str8">str8 rA, rB, rD</h4> 235 <h4 id="str8">str8 rA, rB, rD</h4>
172 <p> 236 <p>
173 Writes the byte stored in rD to the address indicated by the sum of rA and rB. 237 Writes the byte stored in rD to the address indicated by the sum of rA and rB.
174 </p> 238 </p>
175 <p> 239 <p>
176 <strong>Flags:</strong> No change 240 <strong>Flags:</strong> No change
177 </p> 241 </p>
242 <p>
243 <strong>Encoding:</strong>
244 <table>
245 <tr>
246 <th>15-12</th>
247 <th>11-8</th>
248 <th>7-4</th>
249 <th>3-0</th>
250 </tr>
251 <tr>
252 <td>Register containing value to write (aka rD)</td>
253 <td>Source A register</td>
254 <td>Source B register</td>
255 <td>$4</th>
256 </tr>
257 </table>
258 </p>
178 <h4 id="str16">str16 rA, rB, rD</h4> 259 <h4 id="str16">str16 rA, rB, rD</h4>
179 <p> 260 <p>
180 Writes the word stored in rD to the address indicated by the sum of rA and rB. 261 Writes the word stored in rD to the address indicated by the sum of rA and rB.
181 </p> 262 </p>
182 <p> 263 <p>
183 <strong>Flags:</strong> No change 264 <strong>Flags:</strong> No change
184 </p> 265 </p>
266 <p>
267 <strong>Encoding:</strong>
268 <table>
269 <tr>
270 <th>15-12</th>
271 <th>11-8</th>
272 <th>7-4</th>
273 <th>3-0</th>
274 </tr>
275 <tr>
276 <td>Register containing value to write (aka rD)</td>
277 <td>Source A register</td>
278 <td>Source B register</td>
279 <td>$5</th>
280 </tr>
281 </table>
282 </p>
185 <h4 id="add">add rA, rB, rD</h4> 283 <h4 id="add">add rA, rB, rD</h4>
186 <p> 284 <p>
187 Adds rA and rB. The result is stored in rD. 285 Adds rA and rB. The result is stored in rD.
188 </p> 286 </p>
189 <p> 287 <p>
190 <strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero 288 <strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero
191 </p> 289 </p>
290 <p>
291 <strong>Encoding:</strong>
292 <table>
293 <tr>
294 <th>15-12</th>
295 <th>11-8</th>
296 <th>7-4</th>
297 <th>3-0</th>
298 </tr>
299 <tr>
300 <td>Destination register</td>
301 <td>Source A register</td>
302 <td>Source B register</td>
303 <td>$6</th>
304 </tr>
305 </table>
306 </p>
192 <h4 id="adc">adc rA, rB, rD</h4> 307 <h4 id="adc">adc rA, rB, rD</h4>
193 <p> 308 <p>
194 Adds rA, rB and the carry flag. The result is stored in rD. 309 Adds rA, rB and the carry flag. The result is stored in rD.
195 </p> 310 </p>
196 <p> 311 <p>
312 <strong>Encoding:</strong>
313 <table>
314 <tr>
315 <th>15-12</th>
316 <th>11-8</th>
317 <th>7-4</th>
318 <th>3-0</th>
319 </tr>
320 <tr>
321 <td>Destination register</td>
322 <td>Source A register</td>
323 <td>Source B register</td>
324 <td>$7</th>
325 </tr>
326 </table>
327 </p>
328 <p>
197 <strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero 329 <strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero
198 </p> 330 </p>
199 <h4 id="and">and rA, rB, rD</h4> 331 <h4 id="and">and rA, rB, rD</h4>
200 <p> 332 <p>
201 Bitwise and of rA and rB is stored in rD. 333 Bitwise and of rA and rB is stored in rD.
202 </p> 334 </p>
203 <p> 335 <p>
204 <strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero 336 <strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero
205 </p> 337 </p>
338 <p>
339 <strong>Encoding:</strong>
340 <table>
341 <tr>
342 <th>15-12</th>
343 <th>11-8</th>
344 <th>7-4</th>
345 <th>3-0</th>
346 </tr>
347 <tr>
348 <td>Destination register</td>
349 <td>Source A register</td>
350 <td>Source B register</td>
351 <td>$8</th>
352 </tr>
353 </table>
354 </p>
206 <h4 id="or">or rA, rB, rD</h4> 355 <h4 id="or">or rA, rB, rD</h4>
207 <p> 356 <p>
208 Bitwise or of rA and rB is stored in rD. 357 Bitwise or of rA and rB is stored in rD.
209 </p> 358 </p>
210 <p> 359 <p>
211 <strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero 360 <strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero
212 </p> 361 </p>
362 <p>
363 <strong>Encoding:</strong>
364 <table>
365 <tr>
366 <th>15-12</th>
367 <th>11-8</th>
368 <th>7-4</th>
369 <th>3-0</th>
370 </tr>
371 <tr>
372 <td>Destination register</td>
373 <td>Source A register</td>
374 <td>Source B register</td>
375 <td>$9</th>
376 </tr>
377 </table>
378 </p>
213 <h4 id="xor">xor rA, rB, rD</h4> 379 <h4 id="xor">xor rA, rB, rD</h4>
214 <p> 380 <p>
215 Bitwise exclusive or of rA and rB is stored in rD. 381 Bitwise exclusive or of rA and rB is stored in rD.
216 </p> 382 </p>
217 <p> 383 <p>
218 <strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero 384 <strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero
219 </p> 385 </p>
386 <p>
387 <strong>Encoding:</strong>
388 <table>
389 <tr>
390 <th>15-12</th>
391 <th>11-8</th>
392 <th>7-4</th>
393 <th>3-0</th>
394 </tr>
395 <tr>
396 <td>Destination register</td>
397 <td>Source A register</td>
398 <td>Source B register</td>
399 <td>$A</th>
400 </tr>
401 </table>
402 </p>
220 <h4 id="lsl">lsl rA, rB, rD</h4> 403 <h4 id="lsl">lsl rA, rB, rD</h4>
221 <p> 404 <p>
222 The value in rA is shifted left by rB bits and stored in rD 405 The value in rA is shifted left by rB bits and stored in rD
223 </p> 406 </p>
224 <p> 407 <p>
225 <strong>Flags:</strong> C = last bit shifted out of rA, N = result is negative, Z = result is zero 408 <strong>Flags:</strong> C = last bit shifted out of rA, N = result is negative, Z = result is zero
226 </p> 409 </p>
410 <p>
411 <strong>Encoding:</strong>
412 <table>
413 <tr>
414 <th>15-12</th>
415 <th>11-8</th>
416 <th>7-4</th>
417 <th>3-0</th>
418 </tr>
419 <tr>
420 <td>Destination register</td>
421 <td>Source A register</td>
422 <td>Source B register</td>
423 <td>$B</th>
424 </tr>
425 </table>
426 </p>
227 <h4 id="lsr">lsr rA, rB, rD</h4> 427 <h4 id="lsr">lsr rA, rB, rD</h4>
228 <p> 428 <p>
229 The value in rA is shifted right by rB bits and stored in rD 429 The value in rA is shifted right by rB bits and stored in rD
230 </p> 430 </p>
231 <p> 431 <p>
232 <strong>Flags:</strong> C = last bit shifted out of rA, N = result is negative, Z = result is zero 432 <strong>Flags:</strong> C = last bit shifted out of rA, N = result is negative, Z = result is zero
433 </p>
434 <p>
435 <strong>Encoding:</strong>
436 <table>
437 <tr>
438 <th>15-12</th>
439 <th>11-8</th>
440 <th>7-4</th>
441 <th>3-0</th>
442 </tr>
443 <tr>
444 <td>Destination register</td>
445 <td>Source A register</td>
446 <td>Source B register</td>
447 <td>$C</th>
448 </tr>
449 </table>
233 </p> 450 </p>
234 <h4 id="asr">asr rA, rB, rD</h4> 451 <h4 id="asr">asr rA, rB, rD</h4>
235 <p> 452 <p>
236 The value in rA is arithmetically shifted right by rB bits and stored in rD. The most significant bit of rA is copied 453 The value in rA is arithmetically shifted right by rB bits and stored in rD. The most significant bit of rA is copied
237 into the newly shifted bits. This allows asr to be used for signed division by powers of 2 as the sign is preserved. 454 into the newly shifted bits. This allows asr to be used for signed division by powers of 2 as the sign is preserved.
238 </p> 455 </p>
239 <p> 456 <p>
240 <strong>Flags:</strong> C = last bit shifted out of rA, N = result is negative, Z = result is zero 457 <strong>Flags:</strong> C = last bit shifted out of rA, N = result is negative, Z = result is zero
458 </p>
459 <p>
460 <strong>Encoding:</strong>
461 <table>
462 <tr>
463 <th>15-12</th>
464 <th>11-8</th>
465 <th>7-4</th>
466 <th>3-0</th>
467 </tr>
468 <tr>
469 <td>Destination register</td>
470 <td>Source A register</td>
471 <td>Source B register</td>
472 <td>$D</th>
473 </tr>
474 </table>
241 </p> 475 </p>
242 <h4 id="bcc">bCC LABEL</h4> 476 <h4 id="bcc">bCC LABEL</h4>
243 <p> 477 <p>
244 bCC performs a relative branch if the condition indicated by CC is true. It has a range of 131 instructions forward or 478 bCC performs a relative branch if the condition indicated by CC is true. It has a range of 131 instructions forward or
245 124 instructions backwards. CC must be one of the following values 479 124 instructions backwards. CC must be one of the following values
314 Use of CC values greater than 9 will result in an invalid instruction exception. 548 Use of CC values greater than 9 will result in an invalid instruction exception.
315 </p> 549 </p>
316 <p> 550 <p>
317 <strong>Flags:</strong> No change 551 <strong>Flags:</strong> No change
318 </p> 552 </p>
553
554 <p>
555 <strong>Encoding:</strong>
556 <table>
557 <tr>
558 <th>15-12</th>
559 <th>11-4</th>
560 <th>3-0</th>
561 </tr>
562 <tr>
563 <td>CC</td>
564 <td>Signed 8-bit offset. Offset is multiplied by two before being added to PC</td>
565 <td>$E</th>
566 </tr>
567 </table>
568 </p>
319 <h4 id="mov">mov rA, rD</h4> 569 <h4 id="mov">mov rA, rD</h4>
320 <p> 570 <p>
321 Stores the value of rA in rD. This can be used as a return or jump instruction if rD is PC. 571 Stores the value of rA in rD. This can be used as a return or jump instruction if rD is PC.
322 </p> 572 </p>
323 <p> 573 <p>
324 <strong>Flags:</strong> No change 574 <strong>Flags:</strong> No change
325 </p> 575 </p>
576 <p>
577 <strong>Encoding:</strong>
578 <table>
579 <tr>
580 <th>15-12</th>
581 <th>11-8</th>
582 <th>7-4</th>
583 <th>3-0</th>
584 </tr>
585 <tr>
586 <td>Destination register</td>
587 <td>Source A register</td>
588 <td>$0</td>
589 <td>$F</th>
590 </tr>
591 </table>
592 </p>
326 <h4 id="neg">neg rA, rD</h4> 593 <h4 id="neg">neg rA, rD</h4>
327 <p> 594 <p>
328 Calculates the 2s complement of rA and stores it in rD. This can be used in combination with add to implement subtraction. 595 Calculates the 2s complement of rA and stores it in rD. This can be used in combination with add to implement subtraction.
329 </p> 596 </p>
330 <p> 597 <p>
331 <strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero 598 <strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero
332 </p> 599 </p>
600 <p>
601 <strong>Encoding:</strong>
602 <table>
603 <tr>
604 <th>15-12</th>
605 <th>11-8</th>
606 <th>7-4</th>
607 <th>3-0</th>
608 </tr>
609 <tr>
610 <td>Destination register</td>
611 <td>Source A register</td>
612 <td>$1</td>
613 <td>$F</th>
614 </tr>
615 </table>
616 </p>
333 <h4 id="not">not rA, rD</h4> 617 <h4 id="not">not rA, rD</h4>
334 <p> 618 <p>
335 Calculates the 1s complement of rA and stores it in rD. 619 Calculates the 1s complement of rA and stores it in rD.
336 </p> 620 </p>
337 <p> 621 <p>
338 <strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero 622 <strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero
339 </p> 623 </p>
624 <p>
625 <strong>Encoding:</strong>
626 <table>
627 <tr>
628 <th>15-12</th>
629 <th>11-8</th>
630 <th>7-4</th>
631 <th>3-0</th>
632 </tr>
633 <tr>
634 <td>Destination register</td>
635 <td>Source A register</td>
636 <td>$2</td>
637 <td>$F</th>
638 </tr>
639 </table>
640 </p>
340 <h4 id="cmp">cmp rA, rD</h4> 641 <h4 id="cmp">cmp rA, rD</h4>
341 <p> 642 <p>
342 Subtracts rA from rD and discards the result, but still updates flags. 643 Subtracts rA from rD and discards the result, but still updates flags.
343 </p> 644 </p>
344 <p> 645 <p>
345 <strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero 646 <strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero
346 </p> 647 </p>
648 <p>
649 <strong>Encoding:</strong>
650 <table>
651 <tr>
652 <th>15-12</th>
653 <th>11-8</th>
654 <th>7-4</th>
655 <th>3-0</th>
656 </tr>
657 <tr>
658 <td>Destination register</td>
659 <td>Source A register</td>
660 <td>$3</td>
661 <td>$F</th>
662 </tr>
663 </table>
664 </p>
347 <h4 id="call">call rA, rD</h4> 665 <h4 id="call">call rA, rD</h4>
348 <p> 666 <p>
349 Stores the address of the next instruction in rD and sets PC to the value in rA. Used for calling subroutines. 667 Stores the address of the next instruction in rD and sets PC to the value in rA. Used for calling subroutines.
350 </p> 668 </p>
351 <p> 669 <p>
352 <strong>Flags:</strong> No change 670 <strong>Flags:</strong> No change
353 </p> 671 </p>
672 <p>
673 <strong>Encoding:</strong>
674 <table>
675 <tr>
676 <th>15-12</th>
677 <th>11-8</th>
678 <th>7-4</th>
679 <th>3-0</th>
680 </tr>
681 <tr>
682 <td>Destination register</td>
683 <td>Source A register</td>
684 <td>$4</td>
685 <td>$F</th>
686 </tr>
687 </table>
688 </p>
354 <h4 id="swap">swap rA, rD</h4> 689 <h4 id="swap">swap rA, rD</h4>
355 <p> 690 <p>
356 Swaps the values in rA and rD. 691 Swaps the values in rA and rD.
357 </p> 692 </p>
358 <p> 693 <p>
359 <strong>Flags:</strong> No change 694 <strong>Flags:</strong> No change
695 </p>
696 <p>
697 <strong>Encoding:</strong>
698 <table>
699 <tr>
700 <th>15-12</th>
701 <th>11-8</th>
702 <th>7-4</th>
703 <th>3-0</th>
704 </tr>
705 <tr>
706 <td>Destination register</td>
707 <td>Source A register</td>
708 <td>$5</td>
709 <td>$F</th>
710 </tr>
711 </table>
360 </p> 712 </p>
361 <h4 id="in">in rA, rD</h4> 713 <h4 id="in">in rA, rD</h4>
362 <p> 714 <p>
363 Reads a word from the IO port indicated by rA and stores it in rD. 715 Reads a word from the IO port indicated by rA and stores it in rD.
364 </p> 716 </p>