Mercurial > repos > simple16
view simple_console.txt @ 11:04d8efe7a1f0
Initial stab at video output and background color rendering. Fixed address decoding in address port write handler.
author | Michael Pavone <pavone@retrodev.com> |
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date | Sun, 27 Mar 2016 17:36:02 -0700 |
parents | 18b66690ae13 |
children | fb14515266f4 |
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Key: 1 = literal 1 bit 0 = literal 0 bit O = opcode bit D = destination register bit A = source A register bit B = source B register bit DDDD AAAA BBBB OOOO 0: ldim D = destination reg A and B form 8-bit immediate value 1: ldimh D = destination reg A and B form 8-bit immediate value 2: ld8 3: ld16 4: str8 5: str16 6: add 7: adc 8: and 9: or A: xor B: lsl C: lsr D: asr E: bcc F: single source DDDD AAAA OOOO 1111 single source 0: mov 1: neg 2: not 3: cmp 4: call A = register containing pointer to function D = register that will store PC value 5: swap 6: in 7: out 8: ini 9: outi A: addi B: andi C: ori D: ls[lr]i MSB of AAAA determines direction LS 3 bits determines magnitude E: cmpi F: single reg DDDD OOOO 1111 1111 0: reti - return from interrupt, D = register to restore from uer 1: trap 2: trapi 3: getepc 4: setepc 5: getesr 6: setesr 7: getenum 8: setenum 9: getuer A: setuer B: invalid C: invalid D: invalid E: invalid F: invalid Registers: r0 - r12 : general purpose r13 : technically general purpose, but canonically the stack register r14 : PC r15 : status register Special Registers epc - Exception PC - Stores PC value to resume to when entering an exception handler esr - Exception SR - same as above, but for SR eur - Exceptuion User Reg - reg for temporary storage of a reg in a handler, intended to be used for the stack pointer enum - Exception Number - holds the number of the most recent exception IO: Ports 0: Controller 1 1: Controller 2 2: Controller 3 3: Controller 4 4: Channel A Freq Load value for a 16-bit down-counter Polarity of output is switched on transition from 1 to 0 Value is loaded on cycles where counter is 0 Special case value of 0 in this register forces polarity to positive 5: Channel B Freq 6: Channel C Freq 7: Channel D Freq 8: Channel A/B Vol 9: Channel C/D Vol A: Timer Freq B: "Serial" Debug Port C: Write Vertical Scroll : Read Vertical Position MMMM MCCC CCCC CFFF C = coarse scroll bit F = fine scroll bit M = mask bit controls which bits come directly from register and which bits come from the sum of the register and the current line number D: Write Horizontal Scroll : Read Horizontal Position xxxx xxxC CCCC CFFF C = coarse scroll bit F = fine scroll bit x = unused E: Write Dest Address : Read Status F: Write Data : Read ??? Name Table Start Address: 0VVV VVVV VHHH HHH0 V = Coarse scroll bit from vertical scroll value H = Coarse scroll bit from horizontal scroll value VDP Memory Map 0000 - 7FFF = Pattern/Name Table RAM 8000 - FDFF = unused, returns $FFFF FE00 - FEFF = Sprite RAM FF00 - FF7F = Palette RAM FF80 - FFFF = Palette RAM (mirror) Another View - MSB determines whether destination is main RAM For MSB 1 Next 7 MSB determines which special RAM is the destination Only values of 7E and 7F are valid for these bits at present 8 LSB determine offset (1 LSB ignored) Writing to Data port puts value into a one word FIFO Offset within memory type is increment when word is pulled from FIFO Writing to the FIFO when it is full will cause the existing entry to be overwritten Pattern Format: 4bpp in an 8x8 tile arrangement Sprite Table Entry: XXXXXXXX YYYYYYYY IXPVHSNN NNNNNNNN S: size -- 0 = 8x8, 1 = 16x16 P: Palette selector H: Horizontal flip V: Vertical flip I: Priority N: Name X: X position (left of screen = 16, right of screen = ?) Y: Y position (top of screen = 16, bottom of screen = 240) Name Table Entry: IPPVHxNN NNNNNNNN P: Palette selector H: Horizontal flip V: Vertical flip I: Priority N: Name x: Unused, should be set to 0 26.112 MHZ Clock Dot Clock Divider 4 CPU Clock Divider 20 (assuming 1 cycle/instruction, 5 for 4 cycles/instruction) Audio Timer Divider 34 Audio Output Divider 544 Alternatively 13.056 Mhz clock and cut the dividers in half H-Counter goes from 0-415 and then wraps back to zero V-Counter goes from 0-261 and then wraps back to zero V-Counter increments when H-Counter wraps Rendering Process: 208 main VRAM access slots 123 slots for background 160-123 = 37 extra slots during active display 48 slots during inactive display 80 slots for sprite rendering 5 slots remain for refresh or external access Since sprite rendering needs to intrude on active display period, a double buffered line buffer is needed. Useful for VGA compatibility anyway