view simple_console.txt @ 2:6204c81e2933

Revert changes to handling of immediate versions of bitwise instructions. Replace asri with cmpi.
author Michael Pavone <pavone@retrodev.com>
date Wed, 23 Mar 2016 19:19:29 -0700
parents 7e44f7d5810b
children 08b69e3f9f17
line wrap: on
line source

Key:
1 = literal 1 bit
0 = literal 0 bit
O = opcode bit
D = destination register bit
A = source A register bit
B = source B register bit

DDDD AAAA BBBB OOOO

0: ldim
	D = destination reg
	A and B form 8-bit immediate value
1: ldimh
	D = destination reg
	A and B form 8-bit immediate value
2: ld8
3: ld16
4: str8
5: str16
6: add
7: adc
8: and
9: or
A: xor
B: lsl
C: lsr
D: asr 
E: bcc
F: single source



DDDD AAAA OOOO 1111

single source

0: mov
1: neg
2: not
3: cmp
4: call
	A = register containing pointer to function
	D = register that will store PC value
5: swap
6: in
7: out
8: ini
9: outi
A: addi
B: andi
C: ori
D: ls[lr]i
	MSB of AAAA determines direction
	LS 3 bits determines magnitude
E: cmpi
F: single reg


DDDD OOOO 1111 1111  

0: reti - return from interrupt, D = register to restore from uer
1: trap
2: trapi
3: getepc
4: setepc
5: getesr
6: setesr
7: getenum
8: setenum
9: getuer
A: setuer
B: getenum
C: setenum
E: invalid
F: invalid


Registers:

r0 - r12 : general purpose
r13 : technically general purpose, but canonically the stack register
r14 : PC
r15 : status register

IO: Ports

0: Controller 1
1: Controller 2
2: Controller 3
3: Controller 4

4: Channel A Freq
	Load value for a 16-bit down-counter
	Polarity of output is switched on transition from 1 to 0
	Value is loaded on cycles where counter is 0
	Special case value of 0 in this register forces polarity to positive
5: Channel B Freq
6: Channel C Freq
7: Channel D Freq

8: Channel A/B Vol
9: Channel C/D Vol

A: Timer Freq
B: "Serial" Debug Port

D: Write Pallette Address : Read Vertical Position
E: Write Name Table Address : Read Horizontal Position
F: Write Sprite Table Address : Read Status?