Key:
1 = literal 1 bit
0 = literal 0 bit
O = opcode bit
D = destination register bit
A = source A register bit
B = source B register bit

DDDD AAAA BBBB OOOO

0: ldim
	D = destination reg
	A and B form 8-bit immediate value
1: ldimh
	D = destination reg
	A and B form 8-bit immediate value
2: ld8
3: ld16
4: str8
5: str16
6: add
7: adc
8: and
9: or
A: xor
B: lsl
C: lsr
D: asr 
E: bcc
F: single source



DDDD AAAA OOOO 1111

single source

0: mov
1: neg
2: not
3: cmp
4: call
	A = register containing pointer to function
	D = register that will store PC value
5: swap
6: longjmp
	A = register containing pointer to function
	D = register containing new code segment value
7: ini
8: outi
9: addi
A: andi
B: ori
C: xori
D: ls[lr]i
	MSB of AAAA determines direction
	LS 3 bits determines magnitude
E: cmpi
F: single reg


DDDD OOOO 1111 1111  

0: reti - return from interrupt, D = register to restore from uer
1: trapi
2: getepc
3: setepc
4: getepch
5: setepch
6: getesr
7: setesr
8: getenum
9: setenum
A: getuer
B: setuer
C: getvbr
D: setvbr
E: getdatabanks
F: setdatabanks


Registers:

r0 - r12 : general purpose
r13 : technically general purpose, but canonically the stack register
r14 : PC
r15 : status register

Special Registers
epc - Exception PC - Stores PC value to resume to when entering an exception handler
epch - High 7-bits of PC
esr - Exception SR - same as above, but for SR
eur - Exceptuion User Reg - reg for temporary storage of a reg in a handler, intended to be used for the stack pointer
enum - Exception Number - holds the number of the most recent exception
databanks - Holds the upper bytes used for data accesses (MSB = byte for upper half of memory space, LSB = byte for lower half of memory space)

IO: Ports

0: Controller 1
1: Controller 2
2: Reserved
3: Reserved

4: Channel A Freq
	Load value for a 16-bit down-counter
	Polarity of output is switched on transition from 1 to 0
	Value is loaded on cycles where counter is 0
	Special case value of 0 in this register forces polarity to positive, useful for PCM playback
5: Channel B Freq
6: Channel C Freq
7: Channel D Freq

8: Channel A/B Vol
9: Channel C/D Vol

A: Timer Freq
B: "Serial" Debug Port

C: Framebuffer start offset : Read Vertical Position
D: Graphics mode : Read Horizontal Position
	EDVP PSSS SSEE EEEF
	E = 0 display disabled, 1 display enabled
	D = 0 4 bpp, 1 8bpp
	F = 0 front buffer is lower 64K, 1 front buffer is upper 64K
	P = palette select
	S = blanked lines at start of frame
	E = blanked lines at end of frame
E: CRAM update port : Read Status
	1st write determines destination and length
	DDDD DDDD LLLL LLLL
	Next L writes are written to D and subsequent addresses

F: Reserved


Video Hardware:
	128KB of VRAM organized into two 64KB linear framebuffers
	Pixels are 4bpp or 8bbp in chunky format
	256 words of 16-bit CRAM
	In 4bpp mode, P field of graphics mode selects one of 4, 16 color palettes
	S and E fields of mode allow hardware letter boxing, effectively increasing the length of vblank
	F field selects which 64KB framebuffer is used for the active display
	Active buffer is inaccessible to CPU, but CPU has free reign over inactive buffer
	H-Counter goes from 0-415 and then wraps back to zero
	V-Counter goes from 0-261 and then wraps back to zero
	V-Counter increments when H-Counter wraps
	
Memory Map
	23-bit address space
	$0      - $3FFFFF - ROM
	$400000 - $4FFFFF - 128K RAM, mirrored every 128KB
	$500000 - $6FFFFF - Reserved
	$700000 - $7FFFFF - 64KB VRAM back buffer, mirrored every 64KB


26.112 MHZ Clock
Dot Clock Divider 4
CPU Clock Divider 4 (assuming 1 cycle/instruction, 1 for 4 cycles/instruction)
Audio Timer Divider 34
Audio Output Divider 544
Interrupt Timer Divider 32

Alternatively 13.056 Mhz clock and cut the dividers in half