# HG changeset patch
# User Michael Pavone <pavone@retrodev.com>
# Date 1458959183 25200
# Node ID 8170d60f188bf39e7ab507196a248d2e31c08eac
# Parent  08b69e3f9f177496547dc00e19b5add291159b74
Added basic rendering timing outline and made some other minor spec changes

diff -r 08b69e3f9f17 -r 8170d60f188b simple_console.txt
--- a/simple_console.txt	Fri Mar 25 09:06:29 2016 -0700
+++ b/simple_console.txt	Fri Mar 25 19:26:23 2016 -0700
@@ -126,7 +126,7 @@
 	F = fine scroll bit
 	x = unused
 E: Write Dest Address : Read Status
-F: Write Data : Read Data
+F: Write Data : Read ???
 
 
 Name Table Start Address:
@@ -149,8 +149,10 @@
 		Only values of 7E and 7F are valid for these bits at present
 		8 LSB determine offset (1 LSB ignored)
 		
-Writing to Data port puts word into FIFO
+Writing to Data port puts value into a one word FIFO
 Offset within memory type is increment when word is pulled from FIFO
+Writing to the FIFO when it is full will cause the existing entry to be overwritten
+
 
 Pattern Format:
 4bpp in an 8x8 tile arrangement
@@ -195,3 +197,15 @@
 H-Counter goes from 0-415 and then wraps back to zero
 V-Counter goes from 0-261 and then wraps back to zero
 V-Counter increments when H-Counter wraps
+
+Rendering Process:
+208 main VRAM access slots
+123 slots for background
+160-123 = 37 extra slots during active display
+          48 slots during inactive display
+80 slots for sprite rendering
+5 slots remain for refresh or external access
+		  
+Since sprite rendering needs to intrude on active display period,
+a double buffered line buffer is needed. Useful for VGA compatibility anyway
+