# HG changeset patch # User Michael Pavone # Date 1460442951 25200 # Node ID a64e11e48a41d0c28651e85dbd9acb96787b4c40 # Parent 23bea9b9569f136a22c6552cf204eeed83a8e4a5 Added encoding for a bunch of instructions diff -r 23bea9b9569f -r a64e11e48a41 simple16.html --- a/simple16.html Sat Apr 09 00:20:59 2016 -0700 +++ b/simple16.html Mon Apr 11 23:35:51 2016 -0700 @@ -147,6 +147,21 @@

Flags: No change

+

+ Encoding: + + + + + + + + + + +
15-1211-43-0
Destination register8-bit immediate value$0 +
+

lidmh IM, rD

ldimh assigns an 8-bit immediate value to the upper 8-bits of rD. @@ -154,6 +169,21 @@

Flags: No change

+

+ Encoding: + + + + + + + + + + +
15-1211-43-0
Destination register8-bit immediate value$1 +
+

ld8 rA, rB, rD

Reads a byte from the address indicated by the sum of rA and rB and loads it into rD @@ -161,6 +191,23 @@

Flags: No change

+

+ Encoding: + + + + + + + + + + + + +
15-1211-87-43-0
Destination registerSource A registerSource B register$2 +
+

ld16 rA, rB, rD

Reads a word from the address indicated by the sum of rA and rB and loads it into rD @@ -168,6 +215,23 @@

Flags: No change

+

+ Encoding: + + + + + + + + + + + + +
15-1211-87-43-0
Destination registerSource A registerSource B register$3 +
+

str8 rA, rB, rD

Writes the byte stored in rD to the address indicated by the sum of rA and rB. @@ -175,6 +239,23 @@

Flags: No change

+

+ Encoding: + + + + + + + + + + + + +
15-1211-87-43-0
Register containing value to write (aka rD)Source A registerSource B register$4 +
+

str16 rA, rB, rD

Writes the word stored in rD to the address indicated by the sum of rA and rB. @@ -182,6 +263,23 @@

Flags: No change

+

+ Encoding: + + + + + + + + + + + + +
15-1211-87-43-0
Register containing value to write (aka rD)Source A registerSource B register$5 +
+

add rA, rB, rD

Adds rA and rB. The result is stored in rD. @@ -189,11 +287,45 @@

Flags: C = carry out of bit 15, N = result is negative, Z = result is zero

+

+ Encoding: + + + + + + + + + + + + +
15-1211-87-43-0
Destination registerSource A registerSource B register$6 +
+

adc rA, rB, rD

Adds rA, rB and the carry flag. The result is stored in rD.

+ Encoding: + + + + + + + + + + + + +
15-1211-87-43-0
Destination registerSource A registerSource B register$7 +
+

+

Flags: C = carry out of bit 15, N = result is negative, Z = result is zero

and rA, rB, rD

@@ -203,6 +335,23 @@

Flags: C = unmodified, N = result is negative, Z = result is zero

+

+ Encoding: + + + + + + + + + + + + +
15-1211-87-43-0
Destination registerSource A registerSource B register$8 +
+

or rA, rB, rD

Bitwise or of rA and rB is stored in rD. @@ -210,6 +359,23 @@

Flags: C = unmodified, N = result is negative, Z = result is zero

+

+ Encoding: + + + + + + + + + + + + +
15-1211-87-43-0
Destination registerSource A registerSource B register$9 +
+

xor rA, rB, rD

Bitwise exclusive or of rA and rB is stored in rD. @@ -217,6 +383,23 @@

Flags: C = unmodified, N = result is negative, Z = result is zero

+

+ Encoding: + + + + + + + + + + + + +
15-1211-87-43-0
Destination registerSource A registerSource B register$A +
+

lsl rA, rB, rD

The value in rA is shifted left by rB bits and stored in rD @@ -224,6 +407,23 @@

Flags: C = last bit shifted out of rA, N = result is negative, Z = result is zero

+

+ Encoding: + + + + + + + + + + + + +
15-1211-87-43-0
Destination registerSource A registerSource B register$B +
+

lsr rA, rB, rD

The value in rA is shifted right by rB bits and stored in rD @@ -231,6 +431,23 @@

Flags: C = last bit shifted out of rA, N = result is negative, Z = result is zero

+

+ Encoding: + + + + + + + + + + + + +
15-1211-87-43-0
Destination registerSource A registerSource B register$C +
+

asr rA, rB, rD

The value in rA is arithmetically shifted right by rB bits and stored in rD. The most significant bit of rA is copied @@ -239,6 +456,23 @@

Flags: C = last bit shifted out of rA, N = result is negative, Z = result is zero

+

+ Encoding: + + + + + + + + + + + + +
15-1211-87-43-0
Destination registerSource A registerSource B register$D +
+

bCC LABEL

bCC performs a relative branch if the condition indicated by CC is true. It has a range of 131 instructions forward or @@ -316,6 +550,22 @@

Flags: No change

+ +

+ Encoding: + + + + + + + + + + +
15-1211-43-0
CCSigned 8-bit offset. Offset is multiplied by two before being added to PC$E +
+

mov rA, rD

Stores the value of rA in rD. This can be used as a return or jump instruction if rD is PC. @@ -323,6 +573,23 @@

Flags: No change

+

+ Encoding: + + + + + + + + + + + + +
15-1211-87-43-0
Destination registerSource A register$0$F +
+

neg rA, rD

Calculates the 2s complement of rA and stores it in rD. This can be used in combination with add to implement subtraction. @@ -330,6 +597,23 @@

Flags: C = carry out of bit 15, N = result is negative, Z = result is zero

+

+ Encoding: + + + + + + + + + + + + +
15-1211-87-43-0
Destination registerSource A register$1$F +
+

not rA, rD

Calculates the 1s complement of rA and stores it in rD. @@ -337,6 +621,23 @@

Flags: C = unmodified, N = result is negative, Z = result is zero

+

+ Encoding: + + + + + + + + + + + + +
15-1211-87-43-0
Destination registerSource A register$2$F +
+

cmp rA, rD

Subtracts rA from rD and discards the result, but still updates flags. @@ -344,6 +645,23 @@

Flags: C = carry out of bit 15, N = result is negative, Z = result is zero

+

+ Encoding: + + + + + + + + + + + + +
15-1211-87-43-0
Destination registerSource A register$3$F +
+

call rA, rD

Stores the address of the next instruction in rD and sets PC to the value in rA. Used for calling subroutines. @@ -351,6 +669,23 @@

Flags: No change

+

+ Encoding: + + + + + + + + + + + + +
15-1211-87-43-0
Destination registerSource A register$4$F +
+

swap rA, rD

Swaps the values in rA and rD. @@ -358,6 +693,23 @@

Flags: No change

+

+ Encoding: + + + + + + + + + + + + +
15-1211-87-43-0
Destination registerSource A register$5$F +
+

in rA, rD

Reads a word from the IO port indicated by rA and stores it in rD.