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WIP documentation
author Michael Pavone <pavone@retrodev.com>
date Wed, 06 Apr 2016 12:15:25 -0700
parents 3b7910575a00
children 413e7b9c0db1
files simple16.html
diffstat 1 files changed, 385 insertions(+), 0 deletions(-) [+]
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+<!doctype html>
+<html>
+<head>
+	<style>
+body {
+	font-family: Helvetica, Arial, sans-serif;
+}
+	</style>
+</head>
+<body>
+	<h1>Simple 16</h1>
+	<p>
+	Simple 16 is a toy 16-bit video game console designed with simplicity of implementation in mind. While it is technically a 16-bit system,
+	it's capabilites are in many ways closer to an 8-bit system. Ultimately, the hope is that Simple 16 is simple enough to provide an easy
+	introduction for the novice emudev while still containing all the essential features of an older game console.
+	
+	</p>
+	<h2>Table of Contents</h2>
+	<ul>
+		<li><a href="#cpu">CPU</a>
+			<ul>
+				<li><a href="#cpuover">Overview</a></li>
+				<li><a href="#cpuregs">Registers</a></li>
+				<li><a href="#instructions">Instructions</a></li>
+				<li><a href="#execution">Execution Details</a></li>
+				<li><a href="#interrupts">Exceptions and Interrupts</a></li>
+			</ul>
+		</li>
+		<li><a href="#video">Video</a></li>
+		<li><a href="#audio">Audio</a></li>
+		<li><a href="#timer">Timer</a></li>
+		<li><a href="#controllers">Controllers</a></li>
+		<li><a href="#serial">Serial Port</a></li>
+		<li><a href="#cart">Cartridge</a></li>
+	</ul>
+	<h2 id="cpu">CPU</h2>
+	<h3 id="cpuover">Overview</h3>
+	<p>
+		The Simple 16 CPU is a 16-bit RISC design. It has a main register file of 16 16-bit registers. Additionally, there are five special
+		purpose registers dedicated to exception processing. It has a flag 16-bit addres space. Instructions are a fixed size and are also 16-bits.
+	</p>
+	<h3 id="cpuregs">Registers</h3>
+	<p>
+		The first 14 registers in the main file have no fixed function and are named r0 through r13. r14 serves as the program counter and
+		points to the next instruction to be fetched. More information about instruction fetch and execution can be found in 
+		<a href="#execution">Execution Details</a>. r15 serves as the status register. The status register contains bits corresponding
+		to the result of the last arithmetic instruction and the interrupt mask. The layout of the status register is given below.
+	</p>
+	<table>
+		<tr>
+			<th>Bit</th>
+			<th>Use</th>
+			<th>Notes</th>
+		<tr>
+			<td>15-5</td>
+			<td>Unused</td>
+			<td>Should be set to zero.</td>
+		</tr>
+		<tr>
+			<td>4</td>
+			<td>Negative Flag</td>
+			<td>Indicates the last result was negative.</td>
+		</tr>
+		<tr>
+			<td>3</td>
+			<td>Carry Flag</td>
+			<td>Generally indicates a carry out of bit 15. Last bit shifted out for shift instructions.</td>
+		</tr>
+		<tr>
+			<td>2</td>
+			<td>Zero fFag</td>
+			<td>Indicates the last result was zero.</td>
+		</tr>
+		<tr>
+			<td>1</td>
+			<td>Interrupt 1 enable</td>
+			<td>Interrupt 1 can be taken when this bit is set.</td>
+		</tr>
+		<tr>
+			<td>0</td>
+			<td>Interrupt 0 enable</td>
+			<td>Interrupt 0 can be taken when this bit is set.</td>
+		</tr>
+	</table>
+	<h3 id="instructions">Instructions</h3>
+	<ul>
+		<li><a href="#ldim">ldim IM, rD</a></li>
+		<li><a href="#ldimh">ldimh IM, rD</a></li>
+		<li><a href="#ld8">ld8 rA, rB, rD</a></li>
+		<li><a href="#ld16">ld16 rA, rB, rD</a></li>
+		<li><a href="#str8">str8 rA, rB, rD</a></li>
+		<li><a href="#str16">str16 rA, rB, rD</a></li>
+		<li><a href="#add">add rA, rB, rD</a></li>
+		<li><a href="#adc">add rA, rB, rD</a></li>
+		<li><a href="#and">and rA, rB, rD</a></li>
+		<li><a href="#or">or rA, rB, rD</a></li>
+		<li><a href="#xor">xor rA, rB, rD</a></li>
+	</ul>
+	<h4 id="ldim">ldim IM, rD</h4>
+	<p>
+		ldim sign extends an 8-bit immediate value to 16-bits and assigns it to the designated register.
+	</p>
+	<p>
+		<strong>Flags:</strong> No change
+	</p>
+	<h4 id="ldimh">lidmh IM, rD</h4>
+	<p>
+		ldimh assigns an 8-bit immediate value to the upper 8-bits of rD.
+	</p>
+	<p>
+		<strong>Flags:</strong> No change
+	</p>
+	<h4 id="ld8">ld8 rA, rB, rD</h4>
+	<p>
+		Reads a byte from the address indicated by the sum of rA and rB and loads it into rD
+	</p>
+	<p>
+		<strong>Flags:</strong> No change
+	</p>
+	<h4 id="ld16">ld16 rA, rB, rD</h4>
+	<p>
+		Reads a word from the address indicated by the sum of rA and rB and loads it into rD
+	</p>
+	<p>
+		<strong>Flags:</strong> No change
+	</p>
+	<h4 id="str8">str8 rA, rB, rD</h4>
+	<p>
+		Writes the byte stored in rD to the address indicated by the sum of rA and rB.
+	</p>
+	<p>
+		<strong>Flags:</strong> No change
+	</p>
+	<h4 id="str16">str16 rA, rB, rD</h4>
+	<p>
+		Writes the word stored in rD to the address indicated by the sum of rA and rB.
+	</p>
+	<p>
+		<strong>Flags:</strong> No change
+	</p>
+	<h4 id="add">add rA, rB, rD</h4>
+	<p>
+		Adds rA and rB. The result is stored in rD.
+	</p>
+	<p>
+		<strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero
+	</p>
+	<h4 id="adc">adc rA, rB, rD</h4>
+	<p>
+		Adds rA, rB and the carry flag. The result is stored in rD.
+	</p>
+	<p>
+		<strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero
+	</p>
+	<h4 id="and">and rA, rB, rD</h4>
+	<p>
+		Bitwise and of rA and rB is stored in rD.
+	</p>
+	<p>
+		<strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero
+	</p>
+	<h4 id="or">or rA, rB, rD</h4>
+	<p>
+		Bitwise or of rA and rB is stored in rD.
+	</p>
+	<p>
+		<strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero
+	</p>
+	<h4 id="xor">xor rA, rB, rD</h4>
+	<p>
+		Bitwise exclusive or of rA and rB is stored in rD.
+	</p>
+	<p>
+		<strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero
+	</p>
+	<h4 id="lsl">lsl rA, rB, rD</h4>
+	<p>
+		The value in rA is shifted left by rB bits and stored in rD
+	</p>
+	<p>
+		<strong>Flags:</strong> C = last bit shifted out of rA, N = result is negative, Z = result is zero
+	</p>
+	<h4 id="lsr">lsr rA, rB, rD</h4>
+	<p>
+		The value in rA is shifted right by rB bits and stored in rD
+	</p>
+	<p>
+		<strong>Flags:</strong> C = last bit shifted out of rA, N = result is negative, Z = result is zero
+	</p>
+	<h4 id="asr">asr rA, rB, rD</h4>
+	<p>
+		The value in rA is arithmetically shifted right by rB bits and stored in rD. The most significant bit of rA is copied
+		into the newly shifted bits. This allows asr to be used for signed division by powers of 2 as the sign is preserved.
+	</p>
+	<h4 id="bcc">bCC</h4>
+	<p>
+		bCC performs a relative branch if the condition indicated by CC is true. It has a range of 131 instructions forward or
+		124 instructions backwards. CC must be one of the following values
+		<table>
+			<tr>
+				<th>CC</th>
+				<th>Mnemonic</th>
+				<th>Name</th>
+				<th>Description</th>
+			</tr>
+			<tr>
+				<td>0</td>
+				<td>ra</td>
+				<td>bRanch Always</td>
+				<td>Unconditionall branch</td>
+			</tr>
+			<tr>
+				<td>1</td>
+				<td>rf</td>
+				<td>bRanch False</td>
+				<td>Effectively a nop</td>
+			</tr>
+			<tr>
+				<td>2</td>
+				<td>eq</td>
+				<td>EQual</td>
+				<td>Branch if zero flag is 1</td>
+			</tr>
+			<tr>
+				<td>3</td>
+				<td>ne</td>
+				<td>Not Equal</td>
+				<td>Branch if zero flag is 0</td>
+			</tr>
+			<tr>
+				<td>4</td>
+				<td>mi</td>
+				<td>MInus</td>
+				<td>Branch if negative flag is 1</td>
+			</tr>
+			<tr>
+				<td>5</td>
+				<td>pl</td>
+				<td>PLus</td>
+				<td>Branch if negative flag is 0</td>
+			</tr>
+			<tr>
+				<td>6</td>
+				<td>cs</td>
+				<td>Carry Set</td>
+				<td>Branch if carry flag is 1. Unsigned "less than" when used with cmp</td>
+			</tr>
+			<tr>
+				<td>7</td>
+				<td>cc</td>
+				<td>Carry Clear</td>
+				<td>Branch if carry flag is 1. Unsigned "greater or equal" when used with cmp</td>
+			</tr>
+			<tr>
+				<td>8</td>
+				<td>gr</td>
+				<td>Greater</td>
+				<td>Branch if carry flag is 0 and the zero flag is zero. Unsigned "greater" when used with cmp</td>
+			</tr>
+			<tr>
+				<td>9</td>
+				<td>le</td>
+				<td>Less or Equal</td>
+				<td>Branch if carry flag is 1 or the zero flag is 1. Unsigned "lesser or equal" when used with cmp</td>
+			</tr>
+		</table>
+		Use of CC values greater than 9 will result in an invalid instruction exception.
+	</p>
+	<h4 id="mov">mov rA, rD</h4>
+	<p>
+		Stores the value of rA in rD. This can be used as a return or jump instruction if rD is PC.
+	</p>
+	<h4 id="neg">neg rA, rD</h4>
+	<p>
+		Calculates the 2s complement of rA and stores it in rD. This can be used in combination with add to implement subtraction.
+	</p>
+	<h4 id="not">not rA, rD</h4>
+	<p>
+		Calculates the 1s complement of rA and stores it in rD.
+	</p>
+	<h4 id="cmp">cmp rA, rD</h4>
+	<p>
+		Subtracts rA from rD and discards the result, but still updates flags.
+	</p>
+	<h4 id="call">call rA, rD</h4>
+	<p>
+		Stores the address of the next instruction in rD and sets PC to the value in rA. Used for calling subroutines.
+	</p>
+	<h4 id="swap">swap rA, rD</h4>
+	<p>
+		Swaps the values in rA and rD.
+	</p>
+	<h4 id="in">in rA, rD</h4>
+	<p>
+		Reads a word from the IO port indicated by rA and stores it in rD.
+	</p>
+	<h4 id="out">out rA, rD</h4>
+	<p>
+		Writes the word stored in rD to the IO port indicated by rA.
+	</p>
+	<h4 id="ini">ini IM, rD</h4>
+	<p>
+		Reads a word from the IO port indicated by IM and stores it in rD. IM can range from 0 to 15.
+	</p>
+	<h4 id="outi">outi</h4>
+	<p>
+		Writes the word stored in rD to the IO port indicated by IM. IM can range from 0 to 15.
+	</p>
+	<h4 id="addi">addi IM, rD</h4>
+	<p>
+		Adds IM to the value in rD and stores the result in rD. IM range from -8 to -1 or 1 to 8. A value of 0 is used to indicate 8.
+	</p>
+	<h4 id="andi">andi IM, rD</h4>
+	<p>
+		Performs a logical and of  IM and the value in rD and stores the result in rD. IM can range from -8 to -1 or 1 to 8. A value of 0 is used to indicate 8.
+	</p>
+	<h4 id="ori">ori IM, rD</h4>
+	<p>
+		Performs a logical or of  IM and the value in rD and stores the result in rD. IM can range from-8 to -1 or 1 to 8. A value of 0 is used to indicate 8.
+	</p>
+	<h4 id="lsli">lsli IM, rD</h4>
+	<p>
+		Shifts the value in rD IM bits to the left. IM can range from 1 to 8.
+	</p>
+	<h4 id="lsri">lsri IM, rD</h4>
+	<p>
+		Shifts the value in rD IM bits to the right. IM can range from 1 to 8.
+	</p>
+	<h4 id="cmpi">cmpi IM, rd</h4>
+	<p>
+		Subtracts IM from rD and discards the result, but updates flags. IM can range from -8 to 7.
+	</p>
+	<h4 id="reti">reti rD</h4>
+	<p>
+		Sets rD to the value storeed in EUR, SR to the value stored in ESR and PC to the value stored in EPC. This instruction is used for returning from an
+		exception or interrupt.
+	</p>
+	<h4 id="trap">trap rD</h4>
+	<p>
+		Causes an exception to be taken to the vector indicated by rD.
+	</p>
+	<h4 id="trapi">trapi IM</h4>
+	<p>
+		Causes an exception to be taken to the vecotr indicated by IM
+	</p>
+	<h4 id="getepc">getepc rD</h4>
+	<p>
+		Stores the value of EPC in rD.
+	</p>
+	<h4 id="setepc">setepc</h4>
+	<p>
+		Stores the vaule of rD in EPC.
+	</p>
+	<h4 id="getesr">getesr</h4>
+	<p>
+	</p>
+	<h4 id="setesr">setesr</h4>
+	<p>
+	</p>
+	<h4 id="geteur">geteur</h4>
+	<p>
+	</p>
+	<h4 id="seteur">seteur</h4>
+	<p>
+	</p>
+	<h4 id="getenum">getenum</h4>
+	<p>
+	</p>
+	<h4 id="setenum">setenum</h4>
+	<p>
+	</p>
+	<h4 id="getvbr">getvbr</h4>
+	<p>
+	</p>
+	<h4 id="setvbr">setvbr</h4>
+	<p>
+	</p>
+	<h2 id="video">Video</h2>
+	<h2 id="audio">Audio</h2>
+	<h2 id="timer">Timer</h2>
+	<h2 id="controllers">Controllers</h2>
+	<h2 id="serial">Serial Port</h2>
+	<h2 id="cart">Cartridge</h2>
+</body>
+</html>
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