Mercurial > repos > simple16
changeset 42:a64e11e48a41
Added encoding for a bunch of instructions
| author | Michael Pavone <pavone@retrodev.com> |
|---|---|
| date | Mon, 11 Apr 2016 23:35:51 -0700 |
| parents | 23bea9b9569f |
| children | 6e7bfe83d2b0 |
| files | simple16.html |
| diffstat | 1 files changed, 352 insertions(+), 0 deletions(-) [+] |
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--- a/simple16.html Sat Apr 09 00:20:59 2016 -0700 +++ b/simple16.html Mon Apr 11 23:35:51 2016 -0700 @@ -147,6 +147,21 @@ <p> <strong>Flags:</strong> No change </p> + <p> + <strong>Encoding:</strong> + <table> + <tr> + <th>15-12</th> + <th>11-4</th> + <th>3-0</th> + </tr> + <tr> + <td>Destination register</td> + <td>8-bit immediate value</td> + <td>$0</th> + </tr> + </table> + </p> <h4 id="ldimh">lidmh IM, rD</h4> <p> ldimh assigns an 8-bit immediate value to the upper 8-bits of rD. @@ -154,6 +169,21 @@ <p> <strong>Flags:</strong> No change </p> + <p> + <strong>Encoding:</strong> + <table> + <tr> + <th>15-12</th> + <th>11-4</th> + <th>3-0</th> + </tr> + <tr> + <td>Destination register</td> + <td>8-bit immediate value</td> + <td>$1</th> + </tr> + </table> + </p> <h4 id="ld8">ld8 rA, rB, rD</h4> <p> Reads a byte from the address indicated by the sum of rA and rB and loads it into rD @@ -161,6 +191,23 @@ <p> <strong>Flags:</strong> No change </p> + <p> + <strong>Encoding:</strong> + <table> + <tr> + <th>15-12</th> + <th>11-8</th> + <th>7-4</th> + <th>3-0</th> + </tr> + <tr> + <td>Destination register</td> + <td>Source A register</td> + <td>Source B register</td> + <td>$2</th> + </tr> + </table> + </p> <h4 id="ld16">ld16 rA, rB, rD</h4> <p> Reads a word from the address indicated by the sum of rA and rB and loads it into rD @@ -168,6 +215,23 @@ <p> <strong>Flags:</strong> No change </p> + <p> + <strong>Encoding:</strong> + <table> + <tr> + <th>15-12</th> + <th>11-8</th> + <th>7-4</th> + <th>3-0</th> + </tr> + <tr> + <td>Destination register</td> + <td>Source A register</td> + <td>Source B register</td> + <td>$3</th> + </tr> + </table> + </p> <h4 id="str8">str8 rA, rB, rD</h4> <p> Writes the byte stored in rD to the address indicated by the sum of rA and rB. @@ -175,6 +239,23 @@ <p> <strong>Flags:</strong> No change </p> + <p> + <strong>Encoding:</strong> + <table> + <tr> + <th>15-12</th> + <th>11-8</th> + <th>7-4</th> + <th>3-0</th> + </tr> + <tr> + <td>Register containing value to write (aka rD)</td> + <td>Source A register</td> + <td>Source B register</td> + <td>$4</th> + </tr> + </table> + </p> <h4 id="str16">str16 rA, rB, rD</h4> <p> Writes the word stored in rD to the address indicated by the sum of rA and rB. @@ -182,6 +263,23 @@ <p> <strong>Flags:</strong> No change </p> + <p> + <strong>Encoding:</strong> + <table> + <tr> + <th>15-12</th> + <th>11-8</th> + <th>7-4</th> + <th>3-0</th> + </tr> + <tr> + <td>Register containing value to write (aka rD)</td> + <td>Source A register</td> + <td>Source B register</td> + <td>$5</th> + </tr> + </table> + </p> <h4 id="add">add rA, rB, rD</h4> <p> Adds rA and rB. The result is stored in rD. @@ -189,11 +287,45 @@ <p> <strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero </p> + <p> + <strong>Encoding:</strong> + <table> + <tr> + <th>15-12</th> + <th>11-8</th> + <th>7-4</th> + <th>3-0</th> + </tr> + <tr> + <td>Destination register</td> + <td>Source A register</td> + <td>Source B register</td> + <td>$6</th> + </tr> + </table> + </p> <h4 id="adc">adc rA, rB, rD</h4> <p> Adds rA, rB and the carry flag. The result is stored in rD. </p> <p> + <strong>Encoding:</strong> + <table> + <tr> + <th>15-12</th> + <th>11-8</th> + <th>7-4</th> + <th>3-0</th> + </tr> + <tr> + <td>Destination register</td> + <td>Source A register</td> + <td>Source B register</td> + <td>$7</th> + </tr> + </table> + </p> + <p> <strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero </p> <h4 id="and">and rA, rB, rD</h4> @@ -203,6 +335,23 @@ <p> <strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero </p> + <p> + <strong>Encoding:</strong> + <table> + <tr> + <th>15-12</th> + <th>11-8</th> + <th>7-4</th> + <th>3-0</th> + </tr> + <tr> + <td>Destination register</td> + <td>Source A register</td> + <td>Source B register</td> + <td>$8</th> + </tr> + </table> + </p> <h4 id="or">or rA, rB, rD</h4> <p> Bitwise or of rA and rB is stored in rD. @@ -210,6 +359,23 @@ <p> <strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero </p> + <p> + <strong>Encoding:</strong> + <table> + <tr> + <th>15-12</th> + <th>11-8</th> + <th>7-4</th> + <th>3-0</th> + </tr> + <tr> + <td>Destination register</td> + <td>Source A register</td> + <td>Source B register</td> + <td>$9</th> + </tr> + </table> + </p> <h4 id="xor">xor rA, rB, rD</h4> <p> Bitwise exclusive or of rA and rB is stored in rD. @@ -217,6 +383,23 @@ <p> <strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero </p> + <p> + <strong>Encoding:</strong> + <table> + <tr> + <th>15-12</th> + <th>11-8</th> + <th>7-4</th> + <th>3-0</th> + </tr> + <tr> + <td>Destination register</td> + <td>Source A register</td> + <td>Source B register</td> + <td>$A</th> + </tr> + </table> + </p> <h4 id="lsl">lsl rA, rB, rD</h4> <p> The value in rA is shifted left by rB bits and stored in rD @@ -224,6 +407,23 @@ <p> <strong>Flags:</strong> C = last bit shifted out of rA, N = result is negative, Z = result is zero </p> + <p> + <strong>Encoding:</strong> + <table> + <tr> + <th>15-12</th> + <th>11-8</th> + <th>7-4</th> + <th>3-0</th> + </tr> + <tr> + <td>Destination register</td> + <td>Source A register</td> + <td>Source B register</td> + <td>$B</th> + </tr> + </table> + </p> <h4 id="lsr">lsr rA, rB, rD</h4> <p> The value in rA is shifted right by rB bits and stored in rD @@ -231,6 +431,23 @@ <p> <strong>Flags:</strong> C = last bit shifted out of rA, N = result is negative, Z = result is zero </p> + <p> + <strong>Encoding:</strong> + <table> + <tr> + <th>15-12</th> + <th>11-8</th> + <th>7-4</th> + <th>3-0</th> + </tr> + <tr> + <td>Destination register</td> + <td>Source A register</td> + <td>Source B register</td> + <td>$C</th> + </tr> + </table> + </p> <h4 id="asr">asr rA, rB, rD</h4> <p> The value in rA is arithmetically shifted right by rB bits and stored in rD. The most significant bit of rA is copied @@ -239,6 +456,23 @@ <p> <strong>Flags:</strong> C = last bit shifted out of rA, N = result is negative, Z = result is zero </p> + <p> + <strong>Encoding:</strong> + <table> + <tr> + <th>15-12</th> + <th>11-8</th> + <th>7-4</th> + <th>3-0</th> + </tr> + <tr> + <td>Destination register</td> + <td>Source A register</td> + <td>Source B register</td> + <td>$D</th> + </tr> + </table> + </p> <h4 id="bcc">bCC LABEL</h4> <p> bCC performs a relative branch if the condition indicated by CC is true. It has a range of 131 instructions forward or @@ -316,6 +550,22 @@ <p> <strong>Flags:</strong> No change </p> + + <p> + <strong>Encoding:</strong> + <table> + <tr> + <th>15-12</th> + <th>11-4</th> + <th>3-0</th> + </tr> + <tr> + <td>CC</td> + <td>Signed 8-bit offset. Offset is multiplied by two before being added to PC</td> + <td>$E</th> + </tr> + </table> + </p> <h4 id="mov">mov rA, rD</h4> <p> Stores the value of rA in rD. This can be used as a return or jump instruction if rD is PC. @@ -323,6 +573,23 @@ <p> <strong>Flags:</strong> No change </p> + <p> + <strong>Encoding:</strong> + <table> + <tr> + <th>15-12</th> + <th>11-8</th> + <th>7-4</th> + <th>3-0</th> + </tr> + <tr> + <td>Destination register</td> + <td>Source A register</td> + <td>$0</td> + <td>$F</th> + </tr> + </table> + </p> <h4 id="neg">neg rA, rD</h4> <p> Calculates the 2s complement of rA and stores it in rD. This can be used in combination with add to implement subtraction. @@ -330,6 +597,23 @@ <p> <strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero </p> + <p> + <strong>Encoding:</strong> + <table> + <tr> + <th>15-12</th> + <th>11-8</th> + <th>7-4</th> + <th>3-0</th> + </tr> + <tr> + <td>Destination register</td> + <td>Source A register</td> + <td>$1</td> + <td>$F</th> + </tr> + </table> + </p> <h4 id="not">not rA, rD</h4> <p> Calculates the 1s complement of rA and stores it in rD. @@ -337,6 +621,23 @@ <p> <strong>Flags:</strong> C = unmodified, N = result is negative, Z = result is zero </p> + <p> + <strong>Encoding:</strong> + <table> + <tr> + <th>15-12</th> + <th>11-8</th> + <th>7-4</th> + <th>3-0</th> + </tr> + <tr> + <td>Destination register</td> + <td>Source A register</td> + <td>$2</td> + <td>$F</th> + </tr> + </table> + </p> <h4 id="cmp">cmp rA, rD</h4> <p> Subtracts rA from rD and discards the result, but still updates flags. @@ -344,6 +645,23 @@ <p> <strong>Flags:</strong> C = carry out of bit 15, N = result is negative, Z = result is zero </p> + <p> + <strong>Encoding:</strong> + <table> + <tr> + <th>15-12</th> + <th>11-8</th> + <th>7-4</th> + <th>3-0</th> + </tr> + <tr> + <td>Destination register</td> + <td>Source A register</td> + <td>$3</td> + <td>$F</th> + </tr> + </table> + </p> <h4 id="call">call rA, rD</h4> <p> Stores the address of the next instruction in rD and sets PC to the value in rA. Used for calling subroutines. @@ -351,6 +669,23 @@ <p> <strong>Flags:</strong> No change </p> + <p> + <strong>Encoding:</strong> + <table> + <tr> + <th>15-12</th> + <th>11-8</th> + <th>7-4</th> + <th>3-0</th> + </tr> + <tr> + <td>Destination register</td> + <td>Source A register</td> + <td>$4</td> + <td>$F</th> + </tr> + </table> + </p> <h4 id="swap">swap rA, rD</h4> <p> Swaps the values in rA and rD. @@ -358,6 +693,23 @@ <p> <strong>Flags:</strong> No change </p> + <p> + <strong>Encoding:</strong> + <table> + <tr> + <th>15-12</th> + <th>11-8</th> + <th>7-4</th> + <th>3-0</th> + </tr> + <tr> + <td>Destination register</td> + <td>Source A register</td> + <td>$5</td> + <td>$F</th> + </tr> + </table> + </p> <h4 id="in">in rA, rD</h4> <p> Reads a word from the IO port indicated by rA and stores it in rD.