Mercurial > repos > tabletprog
annotate modules/x86.tp @ 179:75aca5f87969
A bunch of fixes in x86 instruction encoding
author | Mike Pavone <pavone@retrodev.com> |
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date | Sat, 24 Aug 2013 09:56:29 -0700 |
parents | 20b6041a8b23 |
children | 270d31c6c4cd |
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1 { |
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2 regnames <- #["rax" "rcx" "rdx" "rbx" "rsp" "rbp" "rsi" "rdi" "r8" "r9" "r10" "r11" "r12" "r13" "r14" "r15"] |
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3 uppernames <- #["ah" "ch" "dh" "bh"] |
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4 ireg <- :regnum { |
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5 #{ |
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6 num <- { regnum } |
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7 reg <- { regnum and 7u8} |
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8 string <- { regnames get: regnum } |
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9 rm <- :tail { reg or 0xC0u8 | tail } |
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10 validforSize? <- :size { true } |
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11 isInteger? <- { false } |
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12 register? <- { true } |
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13 upper? <- { true } |
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14 needsRex? <- { regnum >= 8u8 } |
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15 rexBitReg <- { |
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16 if: needsRex? { |
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17 4u8 |
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18 } else: { |
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19 0u8 |
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20 } |
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21 } |
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22 rexBitRM <- { |
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23 if: needsRex? { |
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24 1u8 |
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25 } else: { |
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26 0u8 |
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27 } |
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28 } |
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29 = <- :other { |
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30 (not: (other isInteger?)) && (other register?) && (not: (other upper?)) && regnum = (other num) |
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31 } |
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32 } |
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33 } |
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34 |
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35 upper <- :regnum { |
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36 #{ |
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37 num <- { regnum } |
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38 reg <- { regnum } |
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39 string <- { uppernames get: regnum - 4 } |
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40 rm <- :tail { regnum or 0xC0u8 | tail } |
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41 validforSize? <- :size { |
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42 size = byte |
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43 } |
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44 isInteger? <- { false } |
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45 register? <- { true } |
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46 upper? <- { true } |
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47 needsRex? <- { false } |
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48 = <- :other { |
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49 (not: (other isInteger?)) && (other register?) && (other upper?) && regnum = (other num) |
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50 } |
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51 } |
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52 } |
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53 fakesrc <- #{ |
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54 needsRex? <- { false } |
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55 rexBitReg <- { 0u8 } |
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56 rexBitRM <- { 0u8 } |
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57 } |
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58 size <- :s { |
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59 #{ |
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60 num <- { s } |
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61 = <- :other { |
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62 s = (other num) |
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63 } |
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64 > <- :other { |
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65 s > (other num) |
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66 } |
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67 >= <- :other { |
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68 s >= (other num) |
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69 } |
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70 < <- :other { |
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71 s < (other num) |
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72 } |
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73 <= <- :other { |
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74 s <= (other num) |
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75 } |
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76 needsRex? <- { s = 3 } |
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77 rexBit <- { |
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78 if: needsRex? { |
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79 0x08u8 |
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80 } else: { |
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81 0u8 |
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82 } |
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83 } |
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84 } |
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85 } |
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86 byte <- size: 0 |
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87 word <- size: 1 |
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88 dword <- size: 2 |
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89 qword <- size: 3 |
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90 |
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91 size_bit <- :opcode size { |
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92 if: size = byte { |
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93 opcode |
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94 } else: { |
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95 opcode or 1u8 |
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96 } |
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97 } |
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98 opex <- :val { |
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99 #{ |
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100 reg <- { val } |
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101 string <- { "opex " . val} |
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102 } |
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103 } |
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104 |
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105 mod_rm:withTail <- :register regmem :end { |
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106 l <- regmem rm: end |
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107 (l value) or ( lshift: (register reg) by: 3u8) | (l tail) |
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108 } |
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109 |
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110 mod_rm <- :reg rm { |
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111 mod_rm: reg rm withTail: [] |
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112 } |
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113 |
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114 int_op:withTail <- :value size :tail { |
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115 if: size >= dword { |
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116 tail <- (uint8: (rshift: value by: 16u64)) | (uint8: (rshift: value by: 24u64)) | tail |
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117 } |
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118 if: size >= word { |
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119 tail <- (uint8: (rshift: value by: 8u64)) | tail |
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120 } |
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121 (uint8: value) | tail |
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122 } |
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123 int_op <- :value size { |
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124 int_op: value size withTail: [] |
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125 } |
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126 //used for mov instructions that support 64-bit immediate operands/offsets |
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127 int_op64 <- :value size { |
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128 tail <- [] |
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129 if: size = qword { |
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130 tail <- (uint8: (rshift: value by: 32u64)) | (uint8: (rshift: value by: 40u64)) | (uint8: (rshift: value by: 48u64)) | (uint8: (rshift: value by: 56u64)) | tail |
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131 } |
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132 int_op: value size withTail: tail |
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133 } |
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134 |
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135 prefix:withInstruction <- :reg rm size :inst { |
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136 if: size = word { |
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137 inst <- 0x66u8 | inst |
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138 } |
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139 if: (size needsRex?) || (reg needsRex?) || (rm needsRex?) { |
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140 rex <- 0x40u8 or (size rexBit) or (reg rexBitReg) or (rm rexBitRM) |
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141 inst <- rex | inst |
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142 } |
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143 inst |
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144 } |
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145 |
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146 _rax <- ireg: 0u8 |
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147 _rcx <- ireg: 1u8 |
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148 _rdx <- ireg: 2u8 |
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149 _rbx <- ireg: 3u8 |
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150 _rsp <- ireg: 4u8 |
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151 _rbp <- ireg: 5u8 |
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152 _rsi <- ireg: 6u8 |
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153 _rdi <- ireg: 7u8 |
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154 _r8 <- ireg: 8u8 |
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155 _r9 <- ireg: 9u8 |
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156 _r10 <- ireg: 10u8 |
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157 _r11 <- ireg: 11u8 |
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158 _r12 <- ireg: 12u8 |
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159 _r13 <- ireg: 13u8 |
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160 _r14 <- ireg: 14u8 |
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161 _r15 <- ireg: 15u8 |
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162 _ah <- upper: 4u8 |
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163 _ch <- upper: 5u8 |
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164 _dh <- upper: 6u8 |
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165 _bh <- upper: 7u8 |
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166 |
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167 op:withCode:withImmed:withOpEx <- :src dst size :normal :immed :myopex { |
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168 reg <- src |
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169 rm <- dst |
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170 base <- if: (src isInteger?) { |
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171 reg <- fakesrc |
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172 (size_bit: immed size) | (mod_rm: (opex: myopex) dst withTail: (int_op: src size)) |
174
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173 } else: { |
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174 if: (src register?) { |
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175 (size_bit: normal size) | (mod_rm: src dst) |
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176 } else: { |
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177 reg <- dst |
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178 rm <- src |
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179 (size_bit: normal or 0x02u8 size) | (mod_rm: dst src) |
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180 } |
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181 } |
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182 prefix: reg rm size withInstruction: base |
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183 } |
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184 |
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185 op:withCode:withImmed:withImmedRax:withOpEx:withByteExtend <- :src dst size :normal :immed :immedRax :myopex :byteExt { |
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186 reg <- src |
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187 rm <- dst |
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188 if: (src isInteger?) { |
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189 reg <- fakesrc |
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190 base <- if: size > byte && (((src signed?) && src < 128 && src >= -128) || ((not: (src signed?)) && src < 256)) { |
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191 byteExt | (mod_rm: (opex: myopex) dst withTail: [(uint8: src)]) |
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192 } else: { |
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193 if: dst = _rax { |
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194 (size_bit: immedRax size) | (int_op: src size) |
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195 } else: { |
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196 (size_bit: immed size) | (mod_rm: (opex: myopex) dst withTail: (int_op: src size)) |
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197 } |
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198 } |
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199 prefix: reg rm size withInstruction: base |
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200 } else: { |
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201 op: src dst size withCode: normal withImmed: immed withOpEx: myopex |
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202 } |
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203 |
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204 } |
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205 |
174
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206 #{ |
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207 rax <- { _rax } |
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208 rcx <- { _rcx } |
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209 rdx <- { _rdx } |
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210 rbx <- { _rbx } |
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211 rsp <- { _rsp } |
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212 rbp <- { _rbp } |
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213 rsi <- { _rsi } |
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214 rdi <- { _rdi } |
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215 r8 <- { _r8 } |
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216 r9 <- { _r9 } |
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217 r10 <- { _r10 } |
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218 r11 <- { _r11 } |
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219 r12 <- { _r12 } |
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220 r13 <- { _r13 } |
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221 r14 <- { _r14 } |
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222 r15 <- { _r15 } |
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223 ah <- { _ah } |
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224 ch <- { _ch } |
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225 dh <- { _dh } |
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226 bh <- { _bh } |
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227 |
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228 b <- { byte } |
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229 w <- { word } |
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230 d <- { dword } |
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231 q <- { qword } |
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232 |
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233 add <- :src dst size { |
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234 op: src dst size withCode: 0u8 withImmed: 0x80u8 withImmedRax: 0x04u8 withOpEx: 0u8 withByteExtend: 0x83u8 |
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235 } |
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236 |
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237 sub <- :src dst size { |
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238 op: src dst size withCode: 0x28u8 withImmed: 0x80u8 withImmedRax: 0x2Cu8 withOpEx: 5u8 withByteExtend: 0x83u8 |
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239 } |
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240 |
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241 mov <- :src dst size { |
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242 reg <- src |
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243 rm <- dst |
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244 if: (src isInteger?) && (dst register?) { |
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245 opval <- if: size = byte { 0xB0u8 } else: { 0xB8u8 } |
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246 base <- opval | (int_op64: src size) |
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247 prefix: fakesrc rm size withInstruction: base |
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248 } else: { |
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249 op: src dst size withCode: 0x88u8 withImmed: 0xC6u8 withOpEx: 0u8 |
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250 } |
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251 } |
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252 |
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253 ret <- { [ 0xC3u8 ] } |
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254 |
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255 |
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256 main <- { |
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
257 print: ((add: rax r8 b) map: :el { hex: el }) |
8b5829372ad1
Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
258 print: "\n" |
8b5829372ad1
Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
259 print: ((add: r9 rdx w) map: :el { hex: el }) |
8b5829372ad1
Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
260 print: "\n" |
8b5829372ad1
Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
261 print: ((add: rax rbx q) map: :el { hex: el }) |
8b5829372ad1
Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
262 print: "\n" |
8b5829372ad1
Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
263 print: ((add: 25 rax q) map: :el { hex: el }) |
8b5829372ad1
Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
264 print: "\n" |
8b5829372ad1
Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
265 print: ((add: rcx rdx d) map: :el { hex: el }) |
8b5829372ad1
Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
266 print: "\n" |
179
75aca5f87969
A bunch of fixes in x86 instruction encoding
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
267 prog <- #[ |
75aca5f87969
A bunch of fixes in x86 instruction encoding
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
268 mov: rdi rax q |
75aca5f87969
A bunch of fixes in x86 instruction encoding
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
269 sub: 1 rdi q |
75aca5f87969
A bunch of fixes in x86 instruction encoding
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
270 add: rdi rax q |
75aca5f87969
A bunch of fixes in x86 instruction encoding
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
271 ret: |
75aca5f87969
A bunch of fixes in x86 instruction encoding
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
272 ] |
75aca5f87969
A bunch of fixes in x86 instruction encoding
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
273 ba <- bytearray executableFromBytes: prog |
75aca5f87969
A bunch of fixes in x86 instruction encoding
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
274 res <- ba runWithArg: 24u64 |
75aca5f87969
A bunch of fixes in x86 instruction encoding
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
275 print: (string: res) . "\n" |
174
8b5829372ad1
Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
276 0 |
8b5829372ad1
Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
277 } |
8b5829372ad1
Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
278 } |
8b5829372ad1
Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
279 } |