Mercurial > repos > tabletprog
annotate modules/x86.tp @ 174:8b5829372ad1
Initial work on x86 instruction encoding module
author | Mike Pavone <pavone@retrodev.com> |
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date | Wed, 21 Aug 2013 08:00:57 -0700 |
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children | 20b6041a8b23 |
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174
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1 { |
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2 ireg <- :regnum { |
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3 #{ |
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4 num <- { regnum } |
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5 reg <- { regnum and 7u8} |
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6 rm <- :tail { reg or 0xC0u8 | tail } |
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7 validforSize? <- :size { true } |
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8 isInteger? <- { false } |
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9 register? <- { true } |
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10 upper? <- { true } |
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11 needsRex? <- { regnum >= 8u8 } |
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12 rexBitReg <- { |
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13 if: needsRex? { |
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14 4u8 |
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15 } else: { |
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16 0u8 |
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17 } |
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18 } |
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19 rexBitRM <- { |
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20 if: needsRex? { |
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21 1u8 |
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22 } else: { |
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23 0u8 |
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24 } |
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25 } |
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26 = <- :other { |
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27 (not: (other isInteger?)) && (other register?) && (not: (other upper?)) && regnum = (other num) |
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28 } |
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29 } |
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30 } |
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31 |
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32 upper <- :regnum { |
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33 #{ |
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34 num <- { regnum } |
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35 reg <- { regnum } |
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36 rm <- :tail { regnum or 0xC0u8 | tail } |
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37 validforSize? <- :size { |
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38 size = byte |
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39 } |
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40 isInteger? <- { false } |
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41 register? <- { true } |
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42 upper? <- { true } |
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43 needsRex? <- { false } |
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44 = <- :other { |
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45 (not: (other isInteger?)) && (other register?) && (other upper?) && regnum = (other num) |
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46 } |
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47 } |
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48 } |
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49 fakesrc <- #{ |
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50 needsRex? <- { false } |
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51 rexBitReg <- { 0u8 } |
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52 rexBitRM <- { 0u8 } |
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53 } |
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54 size <- :s { |
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55 #{ |
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56 num <- { s } |
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57 = <- :other { |
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58 s = (other num) |
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59 } |
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60 > <- :other { |
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61 s > (other num) |
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62 } |
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63 >= <- :other { |
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64 s >= (other num) |
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65 } |
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66 < <- :other { |
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67 s < (other num) |
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68 } |
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69 <= <- :other { |
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70 s <= (other num) |
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71 } |
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72 needsRex? <- { s = 3 } |
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73 rexBit <- { |
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74 if: needsRex? { |
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75 0x08u8 |
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76 } else: { |
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77 0u8 |
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78 } |
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79 } |
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80 } |
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81 } |
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82 byte <- size: 0 |
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83 word <- size: 1 |
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84 dword <- size: 2 |
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85 qword <- size: 3 |
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86 |
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87 size_bit <- :opcode size { |
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88 if: size = byte { |
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89 opcode |
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90 } else: { |
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91 opcode or 2u8 |
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92 } |
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93 } |
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94 opex <- :val { |
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95 #{ |
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96 reg <- { val } |
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97 } |
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98 } |
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99 |
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100 mod_rm:withTail <- :register regmem :end { |
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101 l <- regmem rm: end |
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102 (l value) or (register reg) | (l tail) |
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103 } |
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104 |
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105 mod_rm <- :reg rm { |
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106 mod_rm: reg rm withTail: [] |
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107 } |
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108 |
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109 int_op <- :value size { |
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110 tail <- [] |
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111 if: size >= dword { |
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112 tail <- (uint8: (value rshift: 16)) | (uint8: (value rshift: 24)) | tail |
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113 } |
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114 if: size >= word { |
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115 tail <- (uint8: (value rshift: 8)) | tail |
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116 } |
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117 (uint8: value) | tail |
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118 } |
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119 |
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120 prefix:withInstruction <- :reg rm size :inst { |
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121 if: size = word { |
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122 inst <- 0x66u8 | inst |
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123 } |
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124 if: (size needsRex?) || (reg needsRex?) || (rm needsRex?) { |
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125 rex <- 0x40u8 or (size rexBit) or (reg rexBitReg) or (rm rexBitRM) |
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126 inst <- rex | inst |
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127 } |
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128 inst |
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129 } |
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130 |
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131 _rax <- ireg: 0u8 |
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132 _rcx <- ireg: 1u8 |
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133 _rdx <- ireg: 2u8 |
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134 _rbx <- ireg: 3u8 |
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135 _rsp <- ireg: 4u8 |
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136 _rbp <- ireg: 5u8 |
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137 _rsi <- ireg: 6u8 |
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138 _rdi <- ireg: 7u8 |
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139 _r8 <- ireg: 8u8 |
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140 _r9 <- ireg: 9u8 |
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141 _r10 <- ireg: 10u8 |
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142 _r11 <- ireg: 11u8 |
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143 _r12 <- ireg: 12u8 |
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144 _r13 <- ireg: 13u8 |
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145 _r14 <- ireg: 14u8 |
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146 _r15 <- ireg: 15u8 |
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147 _ah <- upper: 4u8 |
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148 _ch <- upper: 5u8 |
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149 _dh <- upper: 6u8 |
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150 _bh <- upper: 7u8 |
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151 |
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152 op:withCode:withImmed:withImmedRax:withOpEx:withByteExtend <- :src dst size :normal :immed :immedRax :myopex :byteExt { |
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153 reg <- src |
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154 rm <- dst |
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155 base <- if: (src isInteger?) { |
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156 reg <- fakesrc |
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157 if: size > byte && (((src signed?) && src < 128 && src >= -128) || ((not: (src signed?)) && src < 256)) { |
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158 0x83u8 | (mod_rm: (opex: myopex) dst withTail: [(uint8: src)]) |
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159 } else: { |
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160 if: dst = _rax { |
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161 (size_bit: immedRax size) | (int_op: src size) |
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162 } else: { |
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163 (size_bit: immed size) | (mod_rm: (opex: myopex) dst withTail: (int_op: src size)) |
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164 } |
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165 } |
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166 } else: { |
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167 if: (src register?) { |
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168 (size_bit: normal size) | (mod_rm: src dst) |
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169 } else: { |
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170 reg <- dst |
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171 rm <- src |
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172 (size_bit: normal or 0x02u8 size) | (mod_rm: dst src) |
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173 } |
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174 } |
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175 prefix: reg rm size withInstruction: base |
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176 } |
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177 |
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178 #{ |
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179 rax <- { _rax } |
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180 rcx <- { _rcx } |
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181 rdx <- { _rdx } |
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182 rbx <- { _rbx } |
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183 rsp <- { _rsp } |
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184 rbp <- { _rbp } |
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185 rsi <- { _rsi } |
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186 rdi <- { _rdi } |
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187 r8 <- { _r8 } |
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188 r9 <- { _r9 } |
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189 r10 <- { _r10 } |
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190 r11 <- { _r11 } |
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191 r12 <- { _r12 } |
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192 r13 <- { _r13 } |
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193 r14 <- { _r14 } |
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194 r15 <- { _r15 } |
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195 ah <- { _ah } |
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196 ch <- { _ch } |
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197 dh <- { _dh } |
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198 bh <- { _bh } |
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199 |
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200 b <- { byte } |
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201 w <- { word } |
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202 d <- { dword } |
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203 q <- { qword } |
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204 |
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205 add <- :src dst size { |
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206 op: src dst size withCode: 0u8 withImmed: 0x80u8 withImmedRax: 0x04u8 withOpEx: 0u8 withByteExtend: 0x83u8 |
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207 } |
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208 |
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209 |
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210 main <- { |
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211 print: ((add: rax r8 b) map: :el { hex: el }) |
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212 print: "\n" |
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213 print: ((add: r9 rdx w) map: :el { hex: el }) |
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214 print: "\n" |
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215 print: ((add: rax rbx q) map: :el { hex: el }) |
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216 print: "\n" |
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217 print: ((add: 25 rax q) map: :el { hex: el }) |
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218 print: "\n" |
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219 print: ((add: rcx rdx d) map: :el { hex: el }) |
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220 print: "\n" |
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221 0 |
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222 } |
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223 } |
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224 } |